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United States Patent | 6,263,356 |
Kozaki ,   et al. | July 17, 2001 |
A calculating apparatus performs FFT calculation or IFFT calculation on input data and then outputs the calculated data. An input buffer memory temporarily stores the input data and outputs it to a memory. An output buffer memory temporarily stores the final data of the calculating apparatus and then outputs it to an external source. The input buffer memory or the output buffer memory is provided with an address generating circuit. The address generating circuit sets the write addresses or the read addresses of the data to be stored in either buffer memory in a predetermined order. Thus, the frequency domain of the data in the calculating apparatus is converted without requiring the use of an external circuit.
Inventors: | Kozaki; Yasunari (Tokyo, JP); Ikeda; Yasunari (Kanagawa, JP) |
Assignee: | Sony Corporation (JP) |
Appl. No.: | 081921 |
Filed: | May 20, 1998 |
May 23, 1997[JP] | P09-133380 |
Current U.S. Class: | 708/400; 708/404 |
Intern'l Class: | G06F 015/00 |
Field of Search: | 708/403,404,405,406,407,408,409,400,401,402 |
3673399 | Jun., 1972 | Hancke et al. | 235/156. |
4138730 | Feb., 1979 | Ali | 708/404. |
5471464 | Nov., 1995 | Ikeda | 370/203. |
5606575 | Feb., 1997 | Williams | 375/219. |
5675572 | Oct., 1997 | Hidejima et al. | 370/206. |
5732113 | Mar., 1998 | Schmidl et al. | 375/355. |
New, "Address Generation in Signal/Array Processors", I.E.E.E. Electro, vol. 8 (1983), pp. 1-5. |