Back to EveryPatent.com
United States Patent | 6,258,659 |
Gruening ,   et al. | July 10, 2001 |
A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.
Inventors: | Gruening; Ulrike (Munich, DE); Divakaruni; Ramachandra (Somers, NY); Mandelman; Jack A. (Stomrville, NY); Rupp; Thomas S. (Stomrville, NY) |
Assignee: | International Business Machines Corporation (Armonk, NY) |
Appl. No.: | 725412 |
Filed: | November 29, 2000 |
Current U.S. Class: | 438/243; 257/E21.66; 438/248 |
Intern'l Class: | H01L 021/824.2 |
Field of Search: | 438/239-249,381,386-392 |
5827765 | Oct., 1998 | Stengl et al. | 438/243. |
5981332 | Nov., 1999 | Mandelman et al. | 438/246. |
6150210 | Nov., 2000 | Arnold. |