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United States Patent | 6,255,177 |
Fang ,   et al. | July 3, 2001 |
A fabrication method for a salicide gate is described, wherein the method comprising forming a gate structure on a substrate. The gate structure comprises a polysilicon gate and a selective-deposition dummy layer formed on the polysilicon gate. Source/drain regions are then formed on both sides of the gate structure in the substrate. After this, a dielectric layer is selectively deposited on the substrate, wherein the dielectric layer on the source/drain regions is thicker than the dielectric layer on the anti-reflection layer. A portion of the dielectric layer is removed until the anti-reflection layer is exposed. The anti-reflection layer is subsequently removed, followed by forming a salicide layer on the polysilicon gate to complete the manufacturing of a salicide gate.
Inventors: | Fang; Edberg (Yuanlin Hsien, TW); Hsieh; Wen-Yi (Hsinchu, TW) |
Assignee: | United Microelectronics Corp. (Hsinchu, TW) |
Appl. No.: | 568321 |
Filed: | May 9, 2000 |
Mar 17, 2000[TW] | 89104924 |
Current U.S. Class: | 438/299; 257/E21.199; 438/303; 438/430; 438/595; 438/655; 438/682; 438/695 |
Intern'l Class: | H01L 021/336 |
Field of Search: | 438/299,300,302,231,303-305,430,595,649,655,695,660,664,682 |
5908313 | Jun., 1999 | Chau et al. | 438/299. |
5956590 | Sep., 1999 | Hsieh et al. | 438/303. |
6025241 | Feb., 2000 | Lin et al. | 438/303. |