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| United States Patent |
6,239,485
|
|
Peters
, et al.
|
May 29, 2001
|
Reduced cross-talk noise high density signal interposer with power and
ground wrap
Abstract
An interposer for providing power, ground, and signal connections between
an integrated circuit chip or chips and a substrate. The inventive
interposer includes a signal core and external power/ground connection
wrap. The two sections may be fabricated and tested separately, then
joined together using z-connection technology. The signal core is formed
from a conductive power/ground plane positioned between two dielectric
layers. A patterned metal layer is formed on each dielectric layer. The
two metal layers are interconnected by a through via or post process. The
conductive power/ground plane functions to reduce signal cross-talk
between signal lines formed on the two patterned metal layers. The
power/ground wrap includes an upper substrate positioned above the signal
core and a lower substrate positioned below the signal core. The upper and
lower substrates of the power/ground wrap are formed from a dielectric
film having a patterned metal layer on both sides, with the patterned
layers connected by a through via or post process. The two power/ground
wrap substrates may be formed separately or from one substrate which is
bent into a desired form (e.g., a "U" shape). The two power/ground
substrates are maintained in their proper alignment relative to the signal
core and to each other by edge connectors which are also connected to the
signal core's intermediary power/ground plane.
| Inventors:
|
Peters; Michael G. (Santa Clara, CA);
Wang; Wen-chou Vincent (Cupertino, CA);
Takahashi; Yasuhito (San Jose, CA);
Chou; William (Cupertino, CA);
Lee; Michael G. (San Jose, CA);
Beilin; Solomon (San Carlos, CA)
|
| Assignee:
|
Fujitsu Limited (JP)
|
| Appl. No.:
|
315785 |
| Filed:
|
May 20, 1999 |
| Current U.S. Class: |
257/700; 257/691; 257/698; 257/738; 257/774; 257/778; 257/780; 257/781; 257/E23.062; 257/E23.063; 257/E23.07; 257/E23.079; 257/E23.114; 257/E23.172; 257/E23.173; 257/E23.175; 361/794; 361/795 |
| Intern'l Class: |
H01L 023/12; H01L 023/053 |
| Field of Search: |
257/700,691,781,698,738,778,780,774,777,734,735,736,779
361/794,795
|
References Cited
U.S. Patent Documents
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|
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|
| 5386341 | Jan., 1995 | Olson et al. | 361/749.
|
| 5394303 | Feb., 1995 | Yamaji | 361/749.
|
| 5396034 | Mar., 1995 | Fujita et al. | 174/261.
|
| 5418689 | May., 1995 | Alpaugh et al. | 361/792.
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| 5419038 | May., 1995 | Wang et al. | 29/830.
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|
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|
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|
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|
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|
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|
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|
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|
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|
| Foreign Patent Documents |
| 0506225 A2 | Sep., 1992 | EP | .
|
| 0506225 A3 | Sep., 1992 | EP | .
|
Other References
Craig N. Ernsberger et al. FLEXCON .TM. '96, "Colaminated Multilayer Flip
Chip T-BGA Package Development" 29-43.
Sarah E. Leach et al. 1997 International Symposium on Advanced Packaging
Materials, "Colamination Technology for electronic Packaging Applications"
38-41.
Catherine Gallagher et al. 1997 International Symposium on Advanced
Packaging Materials, "Vertical Interconnect in Multilayer Applications
Using Ormet.RTM. Conductive Composites" 35-37.
Ernsberger Proceedings of the First International Conference on Flex
Circuits, Oct. 10-14, 1994, High Density Multilayer Interconnect Based on
Adhesiveless Flex Circuits.
|
Primary Examiner: Tran; Minh Loan
Assistant Examiner: Thai; Luan
Attorney, Agent or Firm: Brothers; Coudert
Parent Case Text
RELATED APPLICATION
This is a continuation-in-part application of U.S. patent application Ser.
No. 09/191,755, U.S. Pat. No. 6,081,026 entitled "NOISE HIGH DENSITY
SIGNAL INTERPOSER WITH POWER AND GROUND WRAP," filed Nov. 13, 1998,
assigned to the assignee of the present application and the contents of
which is hereby incorporated by reference.
Claims
What is claimed is:
1. An interposer for connecting an integrated circuit chip to a mounting
substrate, comprising:
a power and ground connection routing structure having a first substrate to
which the integrated circuit chip may be interconnected and a second
substrate to which the mounting substrate may be interconnected, the first
and second substrates including a plurality of conductive vias formed
therein for power and ground connection paths between the mounting
substrate and a mounted integrated circuit chip; and
a signal line routing structure disposed between the first and second
substrates of the power and ground connection routing structure, the
signal line routing structure including a conductive substrate on a first
and second sides of which is disposed a dielectric layer, with a patterned
metal layer disposed on each dielectric layer, and including a plurality
of conductive vias formed between the patterned metal layers for signal
paths between the first and second substrates of the power and ground
connection routing structure,
wherein the power and ground connection paths are substantially isolated
from the signal paths so that power is routed through the power and ground
connection routing structure without passing through the signal line
routing structure.
2. The interposer of claim 1, wherein the power and ground connection
routing structure further comprises:
a patterned conductive layer arranged on a first and a second coplanar face
of the first substrate, the conductive vias providing electrical
connections between the conductive layers on the first and second faces of
the first substrate; and
a patterned conductive layer arranged on a first and a second coplanar face
of the second substrate, the conductive vias providing electrical
connections between the conductive layers on the first and second faces of
the second substrate.
3. The interposer of claim 1, further comprising:
a support member to maintain the first and second substrates of the power
and ground connection routing structure at a desired separation.
4. The interposer of claim 3, wherein the support member electrically
connects the conductive substrate of the signal line routing structure to
the power connection paths of the power and ground connection structure.
5. The interposer of claim 2, wherein the power and ground connection
routing structure further comprises:
a ground connection path between the first coplanar face of the first
substrate and the second coplanar face of the second substrate.
6. The interposer of claim 2, wherein the power and ground connection
routing structure further comprises:
a power connection path between the second coplanar face of the first
substrate and the first coplanar face of the second substrate.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit device packaging, and
more specifically, to an interposer substrate capable of reducing
cross-talk between signal lines which is suitable for interconnecting
integrated circuit chips to a printed circuit board or other substrate.
2. Description of the Prior Art
An interposer is a structure used in the manufacture of single and
multi-chip modules (SCMs or MCMs) to electrically connect one or more
integrated circuit chips (ICs) to a printed circuit board or other
substrate. The interposer provides power and ground connections between
the board or substrate and the ICs. The interposer also provides signal
paths between the IC chips and the board or substrate, and if desired,
between different chips mounted on the interposer. An interposer thus
provides a means of interconnecting signal, power, and ground lines
between a substrate, an integrated circuit chip or chips, and ultimately a
package containing the chip(s).
As the number of components in electronic devices increases and the size of
the individual components decreases, there is an increase in the number
and density of power, ground, and signal interconnections needed between
individual ICs and the substrate to which the chips are connected. This
means that the density of the interconnections which need to be included
as part of an interposer also increases. However, problems arise in
placing signal lines in close proximity to each other and to power supply
lines when fabricating such an interposer. These problems include
interference and cross-talk arising from coupling between the lines on a
common layer or between signal lines on different signal layers, and
capacitive coupling between the lines and the substrate which produces
noise in the signals. In conjunction with the separation between the
various lines, the dielectric constant of the substrate material thus
plays an important role in reducing (or creating) these type of problems.
Another disadvantage of conventional approaches to packaging IC chips in
MCMs arises from the method used to deliver power to the chips. This
problem results because power lines are typically routed through the same
substrate which is utilized to carry signals to and from the chip. The
power feedthroughs will compete for space with the signal I/O lines. This
will further increase the problems caused by densely packed signal traces.
Another important disadvantage is that the thinness of the substrates used
in traditional multichip modules results in the power feeds to the IC
chips having a relatively high impedance. This results in undesired noise,
power loss, and excess thermal energy production. These problems are
relevant to the routing of both power and signal lines though an
interposer substrate.
What is desired is an interposer for interconnecting a single integrated
circuit chip to a substrate, or for interconnecting a plurality of chips
to each other and to a substrate, which addresses the noted disadvantages
of conventional structures.
SUMMARY OF THE INVENTION
The present invention is directed to an interposer for providing power,
ground, and signal connections between an integrated circuit chip or chips
and a substrate. The inventive interposer includes a signal core and
external power/ground connection wrap. The two sections may be fabricated
and tested separately, then joined together using z-connection technology.
The signal core is formed from a conductive power/ground plane positioned
between two dielectric layers. A patterned metal layer is formed on each
dielectric layer. The two metal layers are interconnected by a through via
or post process. The conductive power/ground plane functions to reduce
signal cross-talk between signal lines formed on the two patterned metal
layers.
The power/ground wrap includes an upper substrate positioned above the
signal core and a lower substrate positioned below the signal core. The
upper and lower substrates of the power/ground wrap are formed from a
dielectric film having a patterned metal layer on both sides, with the
patterned layers connected by a through via or post process. The two
power/ground wrap substrates may be formed separately or from one
substrate which is bent into a desired form (e.g., a "U" shape). The two
power/ground substrates are maintained in their proper alignment relative
to the signal core and to each other by edge connectors which are also
connected to the signal core's intermediary power/ground plane.
The top layer of the upper power/ground wrap substrate and the bottom layer
of the lower power/ground wrap substrate serve as the ground layer. The
ground layer includes isolated pads for signal and power interconnections
between the base substrate on which the interposer is mounted and the
chip(s) mounted on top of the interposer. The bottom layer of the upper
substrate and the top layer of the lower substrate of the power/ground
wrap serve as the power layer and include isolated pads for signal
interconnections. With an integrated circuit chip or chips connected to
the upper layer of the top substrate of the power/ground wrap and a
printed circuit board or other mounting substrate connected to the bottom
layer of the lower substrate of the wrap, the inventive interposer
provides a set of high density and electrically isolated signal, power,
and ground interconnections having reduced cross-talk between signal
lines.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross-sectional view of the reduced cross-talk signal
interposer of the present invention, and is shown positioned between a
printed circuit board and an integrated circuit chip.
FIG. 2 is a schematic cross-sectional view of the signal core which is part
of the interposer of the present invention.
FIGS. 3(a) to (g) show a process flow for a first method of fabricating the
signal core which is part of the interposer of the present invention.
FIGS. 4(a) to (g) show a process flow for a second method of fabricating
the signal core which is part of the interposer of the present invention.
FIGS. 5(a) to (e) show a process flow for a method of fabricating the
power/ground wrap which is part of the interposer of the present
invention.
FIG. 6 is a schematic cross-sectional view of a different construction of
the reduced cross-talk signal interposer of the present invention, and is
shown positioned between a printed circuit board and an integrated circuit
chip.
DETAILED DESCRIPTION OF THE INVENTION
The present invention is directed to an interposer designed to provide
signal, power, and ground connections between an integrated circuit chip
and an underlying printed circuit board or substrate. The inventive
interposer provides several advantages over conventional structures:
(1) The density of the interposer signal routing lines can be higher than
for conventional interposers because there are no power and ground line
connects which pass through the signal core. In this regard, the gap
between vias which connect signal lines is increased by approximately a
factor of the square root of 2 compared to the line density on a chip.
This means that the signal line density on the interposer can be increased
relative to that on a chip which includes power and ground lines:
(2) Different technology and processes can be used to fabricate the signal
core and the power/ground wrap. Since the pattern size of the power/ground
wrap is larger, a lower cost process (e.g., subtractive) can be used:
(3) The signal core and power/ground wrap can be fabricated and tested
separately. This is advantageous because the cycle time and yield of
parallel processes will be better than for sequential processes:
(4) The power/ground plane positioned between the signal layers on either
side of the signal core acts to reduce the cross-talk between signal lines
on the two layers;
(5) The majority of the power/ground vias can be replaced by an edge
connection. If a laser is used to drill the vias, the need for fewer vias
will reduce the cost of this aspect of the fabrication: and
(6) If a decoupling capacitor or termination resistor is needed, it (they)
can be connected externally through the edge connector of the power/ground
layers in one direction and the edges of the signal layers in another
direction. This will provide a three-dimensional package.
As the inventors have realized, not all of the connections (power, ground,
signal resistor, capacitor, etc.) required to connect an IC chip to a
substrate need to pass through an intermediary interposer or be
distributed on the same substrate. As a result, the signal traces can be
increased in density and the fabrication costs can be reduced by using the
inventive structure.
FIG. 1 is a schematic cross-sectional view of the reduced cross-talk signal
interposer 100 of the present invention, and is shown positioned between a
printed circuit board 102 and an integrated circuit chip 104. The legend
for the figure identifies some of the components of the complete
structure. As shown in the figure, interposer 100 includes two primary
sections; a signal core 106 and a power/ground wrap 108. The two sections
can be fabricated and tested separately and then joined together using a
z-connection technology, e.g., solder bumps, anisotropic conducting
polymers, or another suitable method. This reduces the cycle time for
manufacturing and testing of the structure, and increase the types of
processing techniques which may be used to form the different parts of the
final structure.
As shown in the figure, in accordance with the present invention, power and
ground interconnections are routed between the mounting substrate 102 and
the chip(s) 104 without passing through the signal core 106. On the other
hand, the signal lines are routed between the mounting substrate 102 and
the chip(s) 104 by passing only through the signal core. This architecture
provides electrical isolation between the power, ground, and signal
interconnections (and hence reduces noise and other problems caused by
capacitive coupling between lines) while increasing the density of signal
lines which can be connected between the substrate and chip(s). Signal
core 106 includes a power/ground layer 109 positioned between signal
layers which are on either side of that substrate and together form the
basis for the signal core. Power/ground layer 109 acts to reduce
cross-talk between signal lines on the same or different signal layers of
signal core 106.
As shown in the figure, edge connectors 500 may be used to electrically
connect different ground layers (e.g., the lower surface of the lower
power/ground substrate to the upper surface of the upper power/ground
substrate), different power layers (e.g., the upper surface of the lower
power/ground substrate to the lower surface of the upper power/ground
substrate), or the power/ground layer of the signal core to other ground
or power layers of the interposer. Although a single set of edge
connectors 500 is shown in the figure, note that if the upper and lower
power/ground substrates are fabricated separately (rather than formed from
a flexible substrate which is bent into a "U" shape), then a set of
connectors 500 may be used at both ends of the two power/ground
substrates.
FIG. 2 is a schematic cross-sectional view of signal core 106 which is part
of the interposer of the present invention. Signal core 106 is formed from
a conductive core or substrate 111 through which holes or apertures are
formed. Conductive core 111 is typically formed from a suitable metal and
serves as both a power/ground layer for the interposer and as a
reinforcing structure for the signal layers of signal core 106. A
dielectric film 110 (e.g., Polyimide, BT, etc.) is arranged on both sides
of conductive core 111. Signal lines 113 are defined on a patterned metal
layer formed on each of the two dielectric film layers. The two patterned
metal layers are interconnected as desired by either a through via or a
conductive post structure 112, with the through via or conductive post
being suitable for interconnecting the signal core to other layers of the
interposer structure, or to the mounting substrate or integrated circuit
chips.
Each dielectric layer 110 is typically 25 to 50 microns thick. As noted,
the patterned metal layers include signal lines 113 and vias/signal pads
112. Signal lines 113 are typically 20 microns wide with a pitch of 20
microns. The size/pitch can be reduced further if desired, e.g., to a
width of 5 microns and pitch of 7.5 microns. Signal pads 112 are used to
interconnect signals between layers of the overall mounting
substrate-interposer-chip structure. Signal pads 112 are typically 100
microns wide with a pitch of 350 microns.
FIGS. 3(a) to (g) show a process flow for a first method of fabricating the
signal core which is part of the reduced cross-talk interposer of the
present invention. In the process flow shown in FIG. 3, the metal layers
on the two sides of the core substrate are interconnected by a through
via. As shown in the figures, the process flow begins with a conductive
layer, which may be formed from a suitable metal 202 (FIG. 3(a)). Holes or
apertures are formed in layer 202 at the positions where through vias or
conductive posts will later be formed (FIG. 3(b)). A dielectric layer 204
is then formed on each surface of conductive layer 202. Dielectric layers
204 may be laminated onto each surface of layer 202 (FIGS. 3(c) and 3(d)).
Vias 206 are formed through dielectric layers 204 in the locations
corresponding to the predefined apertures in conductive layer 202 (FIG.
3(e)). Vias 206 may be formed by means of a laser drill or plasma etch
process. Vias 206 are then metallized and a seed layer 208 is deposited on
the surface of each dielectric layer 204 using electroless plating, direct
plating, sputtering, or another suitable process (FIG. 3(f)). Seed layer
208 is then built up to form a metal layer of desired thickness which is
patterned as desired to form signal lines 210 and signal pads 211 (FIG.
3(g)). The metal signal line layer may be patterned using either an
additive process (e.g., electrolytic plating) or a subtractive process.
Note that an additive process may be preferable for some of the steps to
achieve metal patterning of 5-10 microns width and a pitch of 5-10
microns. If the line width or pitch can be larger, a subtractive process
may be used.
FIGS. 4(a) to (g) show a process flow for a second method of fabricating
the signal core which is part of the reduced cross-talk interposer of the
present invention. In the process flow shown in FIG. 4, a conductive layer
202 again has holes or apertures formed through it at desired locations
(FIGS. 4(a) and 4(b)). A dielectric layer 204 is formed (e.g., laminated)
onto one surface of conductive layer 202. A dielectric having a previously
formed metallized surface or layer 205 is then laminated onto the other
surface of conductive layer 202 (FIGS. 4(c) and 4(d)). Vias 206 are formed
through dielectric layers 204 in the locations corresponding to the
predefined apertures in conductive layer 202 (FIG. 4(e)). Vias 206 may be
formed by means of a laser drill or plasma etch process. Metallized layer
207 of the combined dielectric and metal layer structure 205 is used to
provide an electrical connection for plating of vias 206 and formation of
a conductive layer 209 on dielectric layer 204 (FIG. 4(f)). A method for
performing this step is described in U.S. patent application Ser. No.
09/275,543, entitled "Method of Fabrication of Substrate with Via
Connection", filed Mar. 24, 1999, assigned to the assignee of the present
invention and the contents of which is hereby incorporated by reference.
Conductive layers 207 and 209 are then patterned as desired to form signal
lines 210 and signal pads 211 (FIG. 4(g)). The seed layers may be
patterned using either an additive process (e.g., electrolytic plating) or
a subtractive process.
Note that an additive process may be preferable for some of the steps to
achieve metal patterning of 5-10 microns width and a pitch of 5-10
microns. If the line width or pitch can be larger, a subtractive process
may be used.
FIGS. 5(a) to (e) show a process flow for a method of fabricating the
power/ground wrap 108 which is part of the reduced cross-talk interposer
of the present invention. The fabrication process shown begins with a
dielectric substrate 400 (e.g., a dielectric film such as polyimide, as
shown in FIG. 5(a)). Through vias 402 are formed in the substrate at the
desired locations FIG. 5(b)). The vias may be formed by a laser drill,
plasma etching, or another suitable method. The vias are then filled with
a conductive material, and a conductive layer 404 is formed on the upper
and lower surfaces of the substrate (FIG. 5(c)). The upper/outer
conductive surface 430 of the power/ground wrap will be patterned to form
the ground layer of the power/ground wrap, with electrically isolated pads
for signal and power interconnections between the IC chip, interposer, and
substrate. The lower/inner conductive surface 432 of the power/ground wrap
will be patterned to form the power layer of the power/ground wrap, with
electrically isolated pads for signal interconnections between the IC
chip, interposer, and substrate.
Dielectric layer 400 is typically 25 to 50 microns thick. Ground layer 430
provides a continuous ground plane formed from a 5 to 20 micron thick
layer of copper, for example. Ground layer 430 includes isolation rings to
permit power and signal lines to be fed through the layer. The signal 440
and power 442 pads formed on ground layer 430 are typically 100 microns
wide with a pitch of 250 microns. Note that the size or pitch may be
altered if desired since a ground connection via is not needed.
Power layer 432 provides a continuous plane formed from a 5 to 20 micron
thick layer of copper, for example and includes isolation rings to permit
signal lines to be fed through the layer. The signal pads 444 formed on
power layer 432 are typically 100 microns wide with a pitch of 350
microns.
The conductive material used to fill the vias and form the conductive
layers may be applied by an electroless and/or electrolytic plating
process. Metal chemical vapor deposition (MCVD) or another suitable
process may also be used.
After formation, the conductive layers on the upper and lower surfaces of
the substrate are patterned to form the desired power, ground, and signal
connections 406 (FIG. 5(d)). A subtractive process may be used to form the
patterned layers. Since substrate 400 is a thin-film, it may be bent to
form the "U" shaped structure of FIG. 5(e) (or another desired shape) from
that of FIG. 5(d). As noted, the top surface 430 of power/ground wrap 108
forms the ground layer and includes isolated pads for signal 440 and power
442 interconnections. The bottom surface 432 of power/ground wrap 108
forms the power layer and includes isolated pads for signal
interconnections 444.
With the signal core of FIG. 2 inserted between the upper and lower
substrates of the power/ground wrap, signal connections may be made
between the base substrate (element 102 of FIG. 1), the signal core, and
the integrated circuit chip(s) in isolation from the power and ground
connections between the base substrate and the chip(s). This permits an
increase in signal line density and minimization of signal path lengths,
while achieving a high degree of electrical isolation between the
different types of lines. Note that in the design for power/ground wrap
108 shown in the figure, the ground connections are arranged on the
outside surfaces of the wrap, while the power connections are on the
inside surfaces. This acts to isolate the power and ground connections
from each other, as well as from the signal connections which pass through
the signal core.
FIG. 6 is a schematic cross-sectional view of a different construction of
the reduced cross-talk signal interposer of the present invention, and is
shown positioned between a printed circuit board and an integrated circuit
chip. In this situation, the need for precise alignment between the top,
bottom, and sides of the wrap and the signal core (which is present in the
method described previously with respect to FIG. 5) is lessened. Instead,
the top and bottom substrates of the ground/power layers may be fabricated
as separate substrates (instead of being formed by bending a single
flexible substrate) and assembled to the signal core separately. Edge
connectors 500, 502 are used to interconnect the power/ground layers
between the two power/ground substrates and the power/ground layer of the
signal core as needed. Note that for the "wrapped" structure shown in FIG.
1, a single set of edge connectors 500 (on one end of the substrates) is
used to provide the desired interconnections between the power/ground
layers and the power/ground layer of the signal core.
When fabricating the inventive reduced cross-talk signal interposer
structure, the upper power/ground substrate or surface, signal core, and
lower power/ground substrate or surface are interconnected as required
using a suitable z-connection technology, followed by attachment of the
edge connector or connectors to interconnect the power/ground substrates.
A preferred z-connection technology suited for use in constructing the
present invention is described in U.S. patent application Ser. No.
09/192,003, filed Nov. 13.sup.th , 1998, entitled "Multilayer Laminated
Substrates With High Density Interconnects and Methods of Making the
Same", assigned to the assignee of the present invention, and the contents
of which is incorporated by reference.
The integrated circuit chip(s) can be attached to the inventive interposer
by flip chip, TAB (tape automated bonding), flip TAB, wire bonding, or
another suitable method. For most applications, the preferred
interconnection method is a flip chip area array process. The interposer
can be connected to the PCB or other substrate by means of a ball grid
array (BGA).
The inventive interposer structure provides several important advantages
compared to conventional interposers. Firstly, since there are no power
and ground line interconnects passing through the signal core, the signal
routing density can be higher than for conventional interposers. This
occurs because the separation between vias in which signal lines can be
formed in the inventive structure is increased by a factor of
approximately the square root of 2 relative to the separation between
signal, power, or ground lines on a chip. For example, the separation
between signal vias on the interposer becomes approximately 350 microns
for applications with a 250 micron via pitch on the chip. This means that
the signal line routing density can be increased on the interposer
relative to its value for the chip, without introducing significant
cross-talk, etc. (i.e., a signal line pitch of 250 microns on the
interposer corresponds to a smaller, impractical pitch on the chip if all
of the signal, power, and ground lines were fabricated on the chip).
This benefit of the present invention can be understood by reference to the
following diagrams. With S: signal, V: power, and G: ground, the lines on
the chip can be represented as:
S V S V S V
G S G S G S
S V S V S V
.vertline. 250 .mu.m .vertline.
The separation between lines (pitch) is shown as 250 microns, a typical
value.
However, with the inventive interposer structure, the signal core lines can
be represented as:
S S S
S S S
S S S 350 .mu.m
The separation between signal lines is now approximately 350 microns. Thus,
assuming a limitation that the lines must be separated by 250 microns, the
density of signal lines though the signal core can be increased relative
to that of the signal lines on the chip. Since the signal lines pass
through the power/ground layers, the lines are shorter than if they were
required to pass around the power and ground lines. This reduces signal
delays and propagation losses.
Another benefit of the present invention is that because the signal core
and power/ground wrap are fabricated in parallel instead of as part of a
sequential process flow, the two structures can be fabricated and tested
separately. This reduces the cycle time and improves the yield for the
overall process. It also permits different technologies and processes to
be used for the two structures, permitting optimization of the process
flow for each structure (and the associated reduction in processing cost).
In addition, since the majority of the power and ground vias typically
used can be replaced by edge connectors, the number of vias formed is
reduced, reducing the fabrication cost.
Although the present invention has been described with reference to
exemplary materials and processes, it may also be practiced using other
embodiments and variations of the inventive concept. For example, the
signal core as well as the power/ground layers can be fabricated from
flexible films or printed circuit boards (for low cost, low performance
systems). If a printed circuit board is used for the signal core, then due
to the low wiring density, more than one signal core can be laminated to a
support substrate, or to another signal core.
If a decoupling capacitor is required, then a thin film capacitor can be
connected to the power/ground layers externally by connection to the edge
connector in one (x) direction. If a termination resistor is required,
then a thin film resistor can be connected to the edge of the signal
layers externally in another (y) direction.
The inventive structure also exhibits reduced cross-talk between signal
lines in the different layers of the signal core because of the presence
of the power/ground layer in the signal core. This permits greater
flexibility in the signal line routing because of a lessened concern for
cross-talk noise (e.g., mixed signal layers (both X and Y) can be routed
in each signal core layer). This can be a substantial advantage for high
performance applications.
In addition to reducing signal line cross-talk, the power/ground layer of
the signal core also supplies increased rigidity to the flexible signal
core substrate, increasing its positional stability. This results in
reduced uncertainty in the location of the signal vias passing through the
signal core, allowing the use of smaller signal pads. This further
increase the space in which signal lines can be routed for a given via
pitch.
Although the described embodiment of the power/ground wrap has two layers,
the total number of power/ground layers can be greater. Each of the layers
can be connected through the edge connector(s). Note that a flexible edge
insert can be built within the power/ground layers. The flexible edge
insert can be inserted into the edge connector for the purpose of
accommodating problems arising from the non-planarity of the edge
connector.
The signal core can be fabricated using a buildup process if the higher
signal line density justifies the increased fabrication cost. The signal
core and/or power/ground layers can be formed from flexible films or
printed circuit boards (PCB, for lower cost and lower performance
systems). If a PCB is used for the signal core, then multiple such cores
may be laminated together. Thin film capacitors (TFC) may be used as
decoupling capacitors. Thin film resistors (TFR) may be used as
termination resistors. Additional signal layers can be formed into the
structure, with the additional layers being electrically separated from
each other (and the other layers) by a power/ground plane.
The terms and expressions which have been employed herein are used as terms
of description and not of limitation, and there is no intention in the use
of such terms and expressions of excluding equivalents of the features
shown and described, or portions thereof, it being recognized that various
modifications are possible within the scope of the invention claimed.
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