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United States Patent | 6,212,597 |
Conlin ,   et al. | April 3, 2001 |
Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.
Inventors: | Conlin; Richard (Franklin, MA); Wright; Tim (Framingham, MA); Marconi; Peter (Franklin, MA); Chatter; Mukesh (Hopkinton, MA) |
Assignee: | NeoNet LLLC (Marlboro, MA) |
Appl. No.: | 901502 |
Filed: | July 28, 1997 |
Current U.S. Class: | 711/105; 710/20; 710/21; 710/38; 711/149; 711/150; 711/168 |
Intern'l Class: | G06F 012/00 |
Field of Search: | 711/105,131,149,150,168 395/840,841,821,853,858,200.42 |
5410540 | Apr., 1995 | Aiki et al. | 370/60. |
5802580 | Sep., 1998 | McAlpine | 711/149. |
5875470 | Feb., 1999 | Dreibelbis | 711/147. |