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United States Patent | 6,172,520 |
Lawman ,   et al. | January 9, 2001 |
The present invention allows one portion of an FPGA to reconfigure another portion of the same FPGA. The invention makes use of input/output ports that can be connected on the input side to a frame register for loading configuration data into the FPGA. When a portion of the FPGA is to be reconfigured, data are loaded by a portion of the FPGA not being reconfigured into the frame register of the FPGA and addressed to the portion of the FPGA being reconfigured. Loading of the data is accomplished by forming a configuration data stream in the portion of the FPGA not being reconfigured, then applying the configuration data stream to an output buffer of the FPGA and forwarding that data to an input buffer that is connected to a frame register of the FPGA configuration structure.
Inventors: | Lawman; Gary R. (San Jose, CA); New; Bernard J. (Los Gatos, CA) |
Assignee: | Xilinx, Inc. (San Jose, CA) |
Appl. No.: | 249961 |
Filed: | February 12, 1999 |
Current U.S. Class: | 326/38; 326/39; 326/41 |
Intern'l Class: | G06F 007/38 |
Field of Search: | 326/38,39,41 |
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