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United States Patent | 6,162,685 |
Chang | December 19, 2000 |
A flash memory. An oxide layer is on a substrate. A stacked gate is formed on the substrate. A tunnel diffusion region is formed in the substrate next to a first side of the stacked gate. The tunnel diffusion region extends to a portion of the substrate under the stacked gate. A doped region is formed in the substrate next to a second side of the stacked gate. The doped region is distant away from the stacked gate by a lateral distance. An inter-poly dielectric layer covers the tunnel diffusion region, the doped region, and the stacked gate. A polysilicon layer is on the inter-poly dielectric layer and extends perpendicular to the stacked gate.
Inventors: | Chang; Kuang-Yeh (Taipei, TW) |
Assignee: | United Microelectronics Corp. (Hsinchu, TW) |
Appl. No.: | 208720 |
Filed: | December 9, 1998 |
Current U.S. Class: | 438/263; 257/E21.682; 257/E27.103; 438/266; 438/305 |
Intern'l Class: | H01L 021/336 |
Field of Search: | 438/263,259,268,257,266,305 437/43,52,316 |
5587332 | Dec., 1996 | Chang et al. | 437/43. |
5960284 | Sep., 1999 | Lin et al. | 438/268. |
6008089 | Dec., 1999 | Hong | 438/259. |