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United States Patent | 6,159,845 |
Yew ,   et al. | December 12, 2000 |
A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.
Inventors: | Yew; Tri-Rung (Hsinchu Hsien, TW); Lur; Water (Taipei, TW); Chung; Hsien-Ta (Hsinchu, TW) |
Assignee: | United Microelectronics Corp. (Hsinchu, TW); United Silicon Incorporated (Hsinchu, TW) |
Appl. No.: | 395906 |
Filed: | September 11, 1999 |
Current U.S. Class: | 438/637; 257/E21.579; 257/E21.581; 257/E21.583; 257/E21.589; 438/619; 438/624; 438/638; 438/687 |
Intern'l Class: | H01L 021/476.3 |
Field of Search: | 438/620,624,619,687,637,639,702,636 |
5641712 | Jun., 1997 | Grivna | 438/624. |
5837618 | Nov., 1998 | Avanzino | 438/778. |
5872064 | Feb., 1999 | Huff | 438/778. |
5949143 | Sep., 1999 | Bang | 257/758. |