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United States Patent | 6,154,095 |
Shigemori ,   et al. | November 28, 2000 |
An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.
Inventors: | Shigemori; Mikio (Rancho Palos Verdes, CA); Karasawa; Hideo (Minowa-machi, JP); Kano; Toshihiko (Minowa-machi, JP); Ichinose; Kazushige (Nagano-ken, JP) |
Assignee: | Seiko Epson Corporation (Tokyo, JP) |
Appl. No.: | 171812 |
Filed: | January 21, 1999 |
PCT Filed: | February 18, 1998 |
PCT NO: | PCT/JP98/00700 |
371 Date: | January 21, 1999 |
102(e) Date: | January 21, 1999 |
PCT PUB.NO.: | WO98/38744 |
PCT PUB. Date: | September 3, 1998 |
Feb 27, 1997[JP] | 9-044383 |
Current U.S. Class: | 331/16; 331/25; 331/36C; 331/44; 331/74; 331/158; 331/177R; 331/177V; 331/179 |
Intern'l Class: | H03B 005/32; H03L 007/18 |
Field of Search: | 331/16,25,36 C,68,74,158,177 R,179,177 V,44 |
5451912 | Sep., 1995 | Torode | 331/108. |
5608770 | Mar., 1997 | Noguchi et al. | 377/47. |
5877657 | Mar., 1999 | Yoshinaka | 331/16. |
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