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United States Patent | 6,151,667 |
Walters | November 21, 2000 |
A telecommunication device has a processor for processing data and a memory which stores the data. The memory is coupled to the processor by a data bus and an address bus. A first address counter provides an output address to the memory for reading out a desired data having the output address. A count of the first address counter is changed to a current address in response to a control signal from the processor, each time the processor generates a desired address. The current address is provided to the memory as the output address which is also the desired address. A comparator compares the desired address with the output address from a second address counter and outputs a load signal to the first counter when the current address from the second address counter differs from the desired address. The load signal loads the desired address in the first counter over the address bus when the current address differs from the desired address so that the output address is equal to the desired address. If the current address equals the desired address, then the desired address is provided to the memory as the output address from the first address counter without use of the address bus.
Inventors: | Walters; Eckhard (Rothenbach, DE) |
Assignee: | U.S. Philips Corporation (New York, NY) |
Appl. No.: | 931396 |
Filed: | September 16, 1997 |
Sep 21, 1996[DE] | 196 38 772 |
Current U.S. Class: | 711/211; 455/9; 455/127.2; 711/219 |
Intern'l Class: | G06F 012/00 |
Field of Search: | 455/91,115,127,343,9 364/232.7 395/853 371/10.2 711/220,1-6,219,211 |
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