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United States Patent | 6,144,581 |
Diorio ,   et al. | November 7, 2000 |
A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.
Inventors: | Diorio; Christopher J. (Torrance, CA); Mead; Carver A. (Pasadena, CA) |
Assignee: | California Institute of Technology (Pasadena, CA) |
Appl. No.: | 201327 |
Filed: | November 30, 1998 |
Current U.S. Class: | 365/185.03; 257/315; 365/185.01 |
Intern'l Class: | G11C 016/04 |
Field of Search: | 365/185.03,185.01 257/314,315 |
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______________________________________ Ser. No. Filing Date Title ______________________________________ 08/721,261 September 26, 96 An Autozeroing Floating (U.S. Pat. No. 5,875,126) Gate Amplifier 08/690,198 July 26, 96 A Three Terminal Silicon (U.S. Pat. No. 5,825,063) Synaptic Device 08/845,018 April 22, 97 Hole Impact Ionization (U.S. Pat. No. 5,990,512) Mechanism of Hot Electron Injection and Four-Terminal pFET Semiconductor Structure for Long-Term Learning ______________________________________