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United States Patent | 6,144,239 |
Yonemori ,   et al. | November 7, 2000 |
A semiconductor integrated circuit includes a register for storing a designated value and a delay element group for delaying an input signal by a delay quantity set based on the designated value to output the signal delayed by the delay quantity as a delay signal. The semiconductor integrated circuit further includes a PLL circuit for inputting the delay signal and a clock signal and for outputting a phase adjustment signal. In this case, the phase adjustment signal is supplied to the delay element group as the input signal.
Inventors: | Yonemori; Shigeki (Kanagawa, JP); Sezaki; Isao (Kanagawa, JP) |
Assignee: | NEC Corporation (Tokyo, JP) |
Appl. No.: | 102517 |
Filed: | June 22, 1998 |
Jun 24, 1997[JP] | 9-166742 |
Current U.S. Class: | 327/158; 327/161; 375/376 |
Intern'l Class: | H03L 007/06 |
Field of Search: | 327/141,155,156,157,158,159,161,162 375/373-376 |
4941156 | Jul., 1990 | Stern et al. | 375/372. |
5446867 | Aug., 1995 | Young et al. | 713/503. |
5677858 | Oct., 1997 | Takeda et al. | 708/313. |
Foreign Patent Documents | |||
63-217452 | Sep., 1988 | JP. | |
3-52185 | Mar., 1991 | JP. | |
3-205920 | Sep., 1991 | JP. | |
4-82099 | Mar., 1992 | JP. | |
4-318400 | Nov., 1992 | JP. | |
5-88036 | Nov., 1993 | JP. | |
9-161472 | Jun., 1997 | JP. |