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United States Patent | 6,125,050 |
Hofmann ,   et al. | September 26, 2000 |
Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.
Inventors: | Hofmann; Franz (Munchen, DE); Willer; Josef (Riermerling, DE); Reisinger; Hans (Grunwald, DE); Basse; Paul-Werner (Wolfratshausen, DE); Krautschneider; Wolfgang (Hohenthann, DE) |
Assignee: | Siemens Aktiengesellschaft (Munich, DE) |
Appl. No.: | 335365 |
Filed: | June 17, 1999 |
Dec 17, 1996[DE] | 196 52 538 |
Current U.S. Class: | 365/51; 365/63; 365/174; 365/182 |
Intern'l Class: | G11C 005/02 |
Field of Search: | 365/51,63,174,182 |
5311465 | May., 1994 | Mori et al. | 365/174. |
5426605 | Jun., 1995 | Van Berkel et al. | 365/182. |
5745407 | Apr., 1998 | Levy et al. | 365/174. |