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United States Patent | 6,118,696 |
Choi | September 12, 2000 |
A memory cell array of a non-volatile semiconductor memory device includes unit strings grouped into first strings belonging to a first string group and second strings belonging to a second string group. Each unit string has a memory cells for storing data in a non-volatile state. Each first string is coupled between an associated bit line of a first bit line group and a first common source line whereas each second string is coupled between an associated bit line of a second bit line group and a second common source line. The bit lines and the common source lines are made of different conductive layers. In accordance with the invention, it is possible to achieve a less critical layout of sense amplifiers coupled to bit lines while easily performing a photolithography process as required in the manufacture of the memory device.
Inventors: | Choi; Jung-Dal (Suwon, KR) |
Assignee: | Samsung Electronics, Co., Ltd. (Suwon, KR) |
Appl. No.: | 305239 |
Filed: | May 4, 1999 |
Sep 21, 1996[KR] | 96-41483 |
Current U.S. Class: | 365/185.11; 257/E27.103; 365/185.13; 365/185.17 |
Intern'l Class: | G11C 016/04 |
Field of Search: | 365/185.11,185.13,185.17,185.01,185.05,185.07 |
4962481 | Oct., 1990 | Choice et al. | 365/185. |
5295096 | Mar., 1994 | Nakajima | 365/218. |
5392248 | Feb., 1995 | Truong et al. | 365/185. |
5440509 | Aug., 1995 | Momodomi et al. | 365/185. |
5448517 | Sep., 1995 | Iwahashi | 365/185. |
5524094 | Jun., 1996 | Nobukata et al. | 365/185. |
5568421 | Oct., 1996 | Aritome | 365/185. |
5572464 | Nov., 1996 | Iwasa | 365/185. |
5587948 | Dec., 1996 | Nakai | 365/185. |
5596526 | Jan., 1997 | Assar et al. | 365/185. |
5621684 | Apr., 1997 | Jung | 365/185. |
5661682 | Aug., 1997 | Lim et al. | 365/185. |
5734609 | Mar., 1998 | Choi et al. | 365/185. |