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United States Patent | 6,104,076 |
Nakayama ,   et al. | August 15, 2000 |
A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.
Inventors: | Nakayama; Yoshiaki (Okazaki, JP); Maeda; Hiroshi (Kariya, JP); Iida; Makio (Ichinomiya, JP); Fujimoto; Hiroshi (Nagoya, JP); Saitou; Mitsuhiro (Oobu, JP); Imai; Hiroshi (Kariya, JP); Ban; Hiroyuki (Aichi-ken, JP) |
Assignee: | Denso Corporation (Kariya, JP) |
Appl. No.: | 748896 |
Filed: | November 15, 1996 |
Nov 15, 1995[JP] | 7-297148 | |
Jan 22, 1996[JP] | 8-008699 | |
Sep 20, 1996[JP] | 8-250299 |
Intern'l Class: | H01L 029/76; H01L 023/58 |
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Efland et al: "An Optimized Resurf LDMOS Power Device Module Compatible with advanced Logic processes", IEEE; IEDM 1992- pp. m.237-240. |