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United States Patent | 6,104,051 |
Suzawa | August 15, 2000 |
There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.
Inventors: | Suzawa; Hideomi (Kanagawa, JP) |
Assignee: | Semiconductor Energy Laboratory Co., Ltd. (Kanagawa-ken, JP) |
Appl. No.: | 165150 |
Filed: | October 2, 1998 |
Jun 13, 1994[JP] | 6-154177 |
Intern'l Class: | H01L 027/108; H01L 029/76; H01L 029/94; H01L 031/119 |
Field of Search: | 257/59,71,72,296,369,379,350,351 |
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