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United States Patent | 6,103,598 |
Yamagata ,   et al. | August 15, 2000 |
A process for producing a semiconductor substrate is provided which comprises providing a first substrate made of silicon having a porous silicon layer formed thereon by making porous the substrate silicon and a nonporous monocrystalline silicon layer epitaxially grown on the porous silicon layer, laminating the first substrate onto a second substrate in a state that at least one of lamination faces of the first and the second substrates has a silicon oxide layer and the nonporous monocrystalline silicon layer is interposed between the laminated substrates, and removing the porous silicon layer by etching, wherein the porous silicon layer is removed by etching with an etchant which etches the nonporous monocrystalline silicon layer and the silicon oxide layer at respective etching rates of not more than 10 angstroms per minute.
Inventors: | Yamagata; Kenji (Sagamihara, JP); Yonehara; Takao (Atsugi, JP); Sato; Nobuhiko (Yokohama, JP); Sakaguchi; Kiyofumi (Yokohama, JP) |
Assignee: | Canon Kabushiki Kaisha (Tokyo, JP) |
Appl. No.: | 678694 |
Filed: | July 11, 1996 |
Jul 13, 1995[JP] | 7-177189 |
Current U.S. Class: | 438/459; 257/E21.215; 257/E21.563; 257/E21.569; 438/753 |
Intern'l Class: | H01L 021/306 |
Field of Search: | 438/753,756,751,750,749,745,459 |
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5278093 | Jan., 1994 | Yonehara | 437/109. |
5290712 | Mar., 1994 | Sato et al. | 437/24. |
5320907 | Jun., 1994 | Sato | 428/446. |
5363793 | Nov., 1994 | Sato | 117/2. |
5374581 | Dec., 1994 | Ichikawa et al. | 437/62. |
5403751 | Apr., 1995 | Nishida et al. | 437/2. |
5403771 | Apr., 1995 | Nishida et al. | 437/89. |
5457058 | Oct., 1995 | Yonehara | 437/24. |
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Osamu Tabata et al., "Anisotropic etching of silicon in TMAH solutions", Sensors and Actuators A Physical A34 (1992) pp. 51-57. T. Takebe et al., Fundamental Selective Etching Characteristics of HF+H.sub.2 O.sub.2 +H.sub.2 O Mixtures for GaAs, J. Electrochem, Soc., vol. 140, 1993, pp. 1169-1180. G. Bomchil et al., "Porous silicon: The material and its applications to SOI Technologies", Microelectronic Engineering, 1988, pp. 293-310. D.K. Sadana et al., "Nano-Defects in Commercial Bonded SOI and Simox", Proceedings 1994 IEEE International SOI Conference, 1994, pp. 111-114. |