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United States Patent |
6,100,130
|
Iba
,   et al.
|
August 8, 2000
|
Method of manufacturing a semiconductor memory device having a trench
capacitor
Abstract
The invention provides a structure which enables a junction leak current to
be reduced without reducing a capacitor area. A trench is formed in the
surface of a substrate such that it is connected to a conductive region
for a transistor. The structure is characterized by comprising a capacitor
electrode formed on the inner peripheral surface of the trench and having
its upper edge portion located below the conductive region, an insulating
layer projecting inward of the trench at least from the upper edge portion
of the capacitor electrode to the conductive region, thereby narrowing the
diameter of the trench, a capacitor insulating film coated on the
capacitor electrode, and a capacitor electrode filling the trench and
contacting the capacitor insulating film.
Inventors:
|
Iba; Junichiro (Wappingers Falls, NY);
Kohyama; Yusuke (Yokosuka, JP)
|
Assignee:
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Kabushiki Kaisha Toshiba (Kawasaki, JP)
|
Appl. No.:
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825993 |
Filed:
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April 4, 1997 |
Foreign Application Priority Data
Current U.S. Class: |
438/243; 257/E21.651; 438/248 |
Intern'l Class: |
H01L 021/824.2 |
Field of Search: |
257/301,304
438/243,249,386-392
|
References Cited
U.S. Patent Documents
4792834 | Dec., 1988 | Uchida | 257/304.
|
4794434 | Dec., 1988 | Pelley, III | 357/23.
|
4967248 | Oct., 1990 | Shimizu | 357/23.
|
5309008 | May., 1994 | Watanabe | 257/301.
|
5482883 | Jan., 1996 | Rajeevakumar.
| |
Foreign Patent Documents |
0 234 891 | Sep., 1987 | EP.
| |
0 287 056 | Oct., 1988 | EP.
| |
1-192157 | Aug., 1989 | JP.
| |
2-9166 | Jan., 1990 | JP.
| |
Other References
Toru Kaga et al; IEEE Transactions on Electron Devices, dated Aug. 8, 1988,
vol. 35, No. 8, "Half-V.sub.CC Sheath-Plate Capacitor DRAM Cell with
Self-Aligned Buried Plate Wiring" pp. 1257-1263.
|
Primary Examiner: Tsai; Jey
Attorney, Agent or Firm: Banner & Witcoff, Ltd.
Parent Case Text
This application is a division of application Ser. No. 08/715,490 filed
Sep. 18, 1996, now abandoned, which isa continuation of application Ser.
No. 08/305,665 filed Sep. 14, 1994, now abandoned.
Claims
What is claimed is:
1. A method of manufacturing a trench capacitor for a dynamic random access
memory (DRAM) cell, comprising the steps of:
forming a trench in a semiconductor substrate;
forming an insulating film in said trench;
filling said trench with a mask layer;
removing portions of said mask layer and said insulating film which are at
an upper portion of said trench;
removing said mask layer; and
oxidizing a portion of said semiconductor substrate which is at said upper
portion of said trench using the remaining insulating film as a mask,
thereby selectively forming an oxide layer.
2. The method according to claim 1, further comprising the steps of:
removing the remaining insulating film, thereby exposing a portion of said
semiconductor substrate which is in said trench; and
forming a diffusion layer on the exposed surface of said semiconductor
substrate in said trench.
3. The method according to claim 2, further comprising the steps of:
coating a capacitor insulating film on said diffusion layer; and
filling said trench with conductive material which covers the capacitor
insulating film.
4. A method of manufacturing a trench capacitor for a dynamic random access
memory (DRAM) cell, comprising the steps of:
forming a trench in a semiconductor substrate;
forming an insulating film in said trench;
forming a mask layer which covers said insulating film except a portion of
said insulating film at an upper portion of said trench;
removing the portion of said insulating film at said upper portion of said
trench using said mask layer as a mask;
removing said mask layer; and
oxidizing an exposed portion of said semiconductor substrate using a
remaining insulating film as a mask, thereby selectively forming an oxide
layer.
5. A method of manufacturing a trench capacitor for a dynamic random access
memory (DRAM) cell, comprising the steps of:
forming a trench in a semiconductor substrate;
forming an oxide layer on a surface of said trench;
forming an insulating film in said trench;
forming a mask layer which covers said insulating film except a portion of
said insulating film at an upper portion of said trench;
removing the portion of said insulating film at said upper portion of said
trench using said mask layer as a mask, to expose a portion of said oxide
layer;
removing said mask layer; and
oxidizing the exposed portion of said oxide layer using a remaining portion
of said insulating film as a mask, thereby selectively forming an oxide
film.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, more particularly to a
trench capacitor structure of a DRAM (Dynamic Random Access Memory), and
also to a method for manufacturing the structure.
2. Description of the Related Art
An example of a DRAM having a sheath-plate type trench capacitor is known
from "Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried
Plate Wiring" published in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35,
NO. 8, August 1988, and written by Toru KAGA, Yoshifumi KAWAMOTO, Tokuo
KURE, Yoshinobu NAKAGOME, Masakazu AOKI, Hideo SUNAMI, Tohachi MAKINO,
Nagatoshi OHKI and Kiyoo ITOH.
FIG. 1 is a cross sectional view, showing a conventional sheath-plate type
trench capacitor. As is shown in FIG. 1, a trench is formed in a
semiconductor substrate 21 in contact with a field oxide film 1. An area
which includes a trench inner wall oxide film 4, a silicon oxide/silicon
nitride (SiO.sub.2 /SiN) film 10, a polysilicon film 14, a diffusion layer
16 and part of the substrate 21 serves as a gate control diode. When a
potential has been applied to the polysilicon film 14 (or to a polysilicon
film 11 formed in a deep portion of the trench), a depletion layer grows
in the vicinity of a peripheral portion of the trench inner wall oxide
film 4, thereby forming an inversion layer such that it extends from the
diffusion layer 16 along the outer periphery of the trench. As a result,
the amount of a junction leak current between the substrate 21 and the
diffusion layer 16 contacting the polysilicon film 14 increases.
To reduce the influence of the potential applied to the polysilicon films
11 and 14, it is necessary to make the oxide film 4 thick. However,
increasing the thickness of the oxide film 4 inevitably reduces the area
of a capacitor insulating film and hence the capacitance of the trench
capacitor.
In the conventional structure, the potential applied to the polysilicon
film filled in the trench increases the junction leak current between the
substrate and the diffusion layer contacting the polysilicon film. To
avoid this, it is necessary to reduce the capacitance of the capacitor to
some extent. Actually, however, the capacitance is excessively reduced
since an increase in junction leak current is prevented by increasing the
thickness of the trench inner wall oxide film.
SUMMARY OF THE INVENTION
It is the object of the invention to provide a highly reliable
semiconductor device having a sufficient trench capacitor capacitance and
a small junction leak current, and also provide a method for manufacturing
the semiconductor device.
According to an aspect of the invention, there is provided a semiconductor
device constituting a DRAM having a trench capacitor, comprising:
a semiconductor substrate of a first conductivity type;
a conductive region of a second conductivity type formed in a surface
portion of the semiconductor substrate;
a trench formed in a surface portion of the semiconductor substrate,
adjacent to the conductive region;
a first capacitor electrode formed on an inner peripheral surface of the
trench and having an upper edge portion located below the conductive
region;
an insulating layer having a portion which extends from the upper edge
portion of the first capacitor electrode to the conductive region and
projects inward of the trench and narrows the diameter of the trench;
a capacitor insulating film coated on the first capacitor electrode; and
a second capacitor electrode filling the trench such that it contacts the
capacitor insulating film and is electrically connected to the conductive
region.
According to another aspect of the invention, there is provided a method of
manufacturing a semiconductor device constituting a DRAM having a trench
capacitor, comprising the steps of:
forming in a semiconductor substrate a trench having a wall surface to be
able to be oxidized;
coating a material with an oxidation resistance on the wall surface of the
trench except for an upper edge portion thereof; and
oxidizing the upper edge portion of the trench, thereby selectively forming
an insulating layer projecting inward of the trench.
In the invention constructed as above, that portion of the insulating
layer, which extends from the upper edge portion of the first capacitor
electrode to the conductive region and in which junction leak can easily
occur, is formed thick such that it projects inward of the trench, thereby
interrupting at that portion continuous formation of an inversion layer
extending along the outside of the trench.
Additional objects and advantages of the invention will be set forth in the
description which follows, and in part will be obvious from the
description, or may be learned by practice of the invention. The objects
and advantages of the invention may be realized and obtained by means of
the instrumentalities and combinations particularly pointed out in the
appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part
of the specification, illustrate presently preferred embodiments of the
invention, and together with the general description given above and the
detailed description of the preferred embodiments given below, serve to
explain the principles of the invention.
FIG. 1 is a cross sectional view, showing a conventional sheath-plate type
trench capacitor;
FIG. 2 is a cross sectional view, showing a trench capacitor employed in a
DRAM according to a first embodiment of the invention;
FIGS. 3-6 are views, useful in explaining essential steps of a method for
forming the structure shown in FIG. 2;
FIG. 7 is a cross sectional view, showing a trench capacitor employed in a
DRAM according to a second embodiment of the invention;
FIGS. 8-10 are views, useful in explaining essential steps of a method for
forming the structure shown in FIG. 7;
FIG. 11 is a cross sectional view, showing a step for obtaining a structure
shown in FIG. 12;
FIG. 12 is a cross sectional view, showing essential part of a sheath-plate
type trench capacitor employed in a DRAM according to a third embodiment
of the invention;
FIG. 13 is a cross sectional view, showing a step for obtaining a structure
shown in FIG. 14;
FIG. 14 is a cross sectional view, showing essential part of a sheath-plate
type trench capacitor employed in a DRAM according to a fourth embodiment
of the invention;
FIG. 15 is a cross sectional view, showing a first structure of the
substrate of a sheath-plate type trench capacitor of a DRAM corresponding
to the DRAM of FIG. 2 but more specific than the same;
FIG. 16 is a cross sectional view, showing a first structure of the
substrate of a sheath-plate type trench capacitor of a DRAM corresponding
to the DRAM of FIG. 7 but more specific than the same;
FIG. 17 is a cross sectional view, showing a second structure of the
substrate of a sheath-plate type trench capacitor of a DRAM corresponding
to the DRAM of FIG. 2 but more specific than the same; and
FIG. 18 is a cross sectional view, showing a second structure of the
substrate of a sheath-plate type trench capacitor of a DRAM corresponding
to the DRAM of FIG. 7 but more specific than the same.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 2 is a cross sectional view, showing a trench capacitor employed in a
DRAM according to a first embodiment of the invention. As is shown in FIG.
2, the source/drain regions 18 of a memory cell transistor (MOS
transistor) are formed in the p-type surface of a monocrystal silicon
semiconductor substrate 21. Reference numeral 17 denotes the gate
electrode of the transistor. A trench 22 is formed in a portion of the
substrate 21 adjacent to one of the source/drain regions 18. A polysilicon
film 5 is formed in an inner peripheral portion of the trench 22. The film
5 has an upper edge portion located below the source/drain region 18, and
serves as a first capacitor electrode. A SiO.sub.2 film 9 extends from the
upper edge portion of the film 5 to the source/drain region 18 such that
it projects inward, thereby reducing the diameter of the trench 22. A
SiO.sub.2 film 4 having a thickness thinner than the film 9 extends
therefrom and covers the inner periphery of the trench 22. A SiO.sub.2
/SiN film 10 covers the polysilicon film 5 and serves as a capacitor
insulating film. A polysilicon film 11 which serves as a second capacitor
electrode is filled in the trench 22 such that it contacts the SiO.sub.2
/SiN film 10 and the drain region 18.
FIGS. 3-6 are views, useful in explaining essential steps of a method for
forming the sheath-plate type trench capacitor shown in FIG. 2. Referring
first to FIG. 3, the trench 22 which has a depth of 5 .mu.m and a diameter
of 0.5 .mu.m is formed in the p-type surface region of the monocrystal
silicon substrate 21 which is adjacent to the field oxide film 1, using a
SiN film 3 as a mask. Then, the SiO.sub.2 film 4, which has a thickness of
20 nm, is formed on the inner periphery of the trench 22 by oxidation at
high temperature. That part of the SiO.sub.2 film 4 which is formed on the
bottom of the trench 22 is selectively etched by unisotropic etching.
Subsequently, the polysilicon film 5 with a thickness of 50 nm, a SiN film
6 with a thickness of 12 nm and a SiO.sub.2 film 7 with a thickness of 50
nm are deposited in this order by the CVD method. The polysilicon film 5
serving as a capacitor electrode is doped with phosphorus of high density
while or after the film 5 is formed. Thereafter, an exposed portion of the
SiO.sub.2 film 7 is removed by a buffer HF aqueous solution, using as a
mask a resist layer 8 having a thickness of 3 .mu.m and formed on the
bottom of the trench.
Then, as is shown in FIG. 4, the resist layer 8 is removed, and an exposed
portion of the SiN film 6 is removed by a hot H.sub.3 PO.sub.4 aqueous
solution, using as a mask the SiO.sub.2 film 7 shown in FIG. 3.
Subsequently, the SiO.sub.2 film 7 is removed by a buffer HF aqueous
solution. The resultant structure is subjected to a high temperature
thermal oxidation treatment, thereby oxidizing a shallow portion of the
trench exposed after removing the SiN film 6, i.e., an upper edge portion
of the polysilicon film 5. As a result, a SiO.sub.2 film 9 having a
thickness of 50 nm is formed. The remaining SiN film 6 is removed by the
hot H.sub.3 PO.sub.4 aqueous solution. The polysilicon film 5 may be doped
in this stage. Then, a SiN film (10) having a thickness of 10 nm is
deposited by the CVD method, and a surface portion thereof is oxidized by
high temperature oxidation, thereby forming a capacitor insulating film 10
of high quality. Alternatively, the SiN film 6 may not be removed after
forming the SiO.sub.2 film 9, and used as the capacitor insulating film.
Subsequently, a polysilicon film 11 having a thickness of 400 nm is formed
in the trench by the CVD method, thereby almost completely filling the
trench. The film 11 thus formed serves as another capacitor electrode. As
in the case of the polysilicon film 5, phosphorus is injected into the
polysilicon film 11. Thereafter, the polysilicon film 11 is selectively
etched back by isotropic dry etching to have a thickness of 4 .mu.m from
the bottom of the trench. Then, a surface portion of the polysilicon film
11 is oxidized by high temperature oxidation, forming a SiO.sub.2 film 12
with a thickness of 10 nm.
Then, as is shown in FIG. 5, an exposed portion of the SiO.sub.2 /SiN film
10 is selectively etched by the isotropic dry etching. Subsequently, that
surface portion of the SiO.sub.2 film 9 which extends to the upper surface
of the polysilicon film 11 is selectively removed by unisotropic etching,
together with the SiO.sub.2 film 12.
Thereafter, as is shown in FIG. 6, the resultant structure is coated with a
resist layer 13, an opening is formed by a lithography technique to expose
a portion of the trench, and the side wall oxide film 4 is removed by the
use of the buffer HF aqueous solution. Thereafter, a structure as shown in
FIG. 2 is obtained. Specifically, the resist layer 13 is removed, a highly
doped polysilicon film 14 is filled in the trench, and that portion of the
polysilicon film 14 which extends from the surface to the lower end of the
SiN film 3 is removed by the isotropic dry etching. Then, a surface
portion of the polysilicon film 14 is oxidized by thermal oxidation,
thereby forming a SiO.sub.2 film 15 with a thickness of 30 nm. Phosphorus
or arsenic injected in the polysilicon film 14 is diffused to the outside
of the trench, thereby forming a diffusion layer 16. Subsequently, the SiN
film 3 is selectively etched by the isotropic dry etching. Thereafter, a
memory cell of the DRAM is formed by a known technique. Specifically, a
gate electrode 17 is selectively formed on the SiO.sub.2 film 15, and
source/drain regions 18 one of which contacts the diffusion layer 16 are
formed (FIG. 2).
In the above-described embodiment, the SiO.sub.2 film 9 which is located
just below the diffusion layer 16 connecting the polysilicon film 14 to
the substrate 21 (in other words, the film 9 which extends from an upper
edge portion of the polysilicon film 5 serving as a capacitor electrode,
to the diffusion layer 16), and in which junction leak will occur, is
formed to have a thickness thicker than the SiO.sub.2 film 4 which extends
to the bottom of the trench. As a result, an inversion layer along the
outside of the trench is hard to form in the vicinity of the film 9. This
means that the thick SiO.sub.2 film 9 prevents an inversion layer formed
along the outside of the trench from being connected to the diffusion
layer 16 by the influence of a potential applied to the polysilicon film
14 (or 11). Further, since in the embodiment, only the SiO.sub.2 film 9 is
formed thick and the substantial area of the capacitor located under the
film 9 is not reduced, the amount of the junction leak can be restrained
without reducing the capacitance of the trench capacitor.
FIG. 7 is a cross sectional view, showing a sheath-plate type trench
capacitor employed in a DRAM according to a second embodiment of the
invention. As is shown in FIG. 7, source/drain regions 18 for a memory
cell transistor (MOS transistor) are formed in the p-type surface of the
monocrystal silicon semiconductor substrate 21. Reference numeral 19
denotes a gate electrode for the transistor. A trench 23 is formed in that
portion of the substrate 21 which is located adjacent to one of the
source/drain regions 18, and a polysilicon film 5 serving as a first
capacitor electrode is formed on the inner peripheral wall and the bottom
of the trench 23 such that an upper edge portion thereof is located below
the source/drain region 18. A thick SiO.sub.2 film 9 projects inward from
the peripheral wall of the trench such that it narrows the diameter of the
trench 23 in an area ranging from the upper edge portion of the
polysilicon film 5 to the source/drain region 18. Reference numeral 27
denotes a diffusion layer formed around the trench 23 as a result of
diffusion of an impurity injected in the polysilicon film 5. A SiO.sub.2
/SiN film 10 serving as a capacitor insulating film is formed on the
polysilicon film 5. A polysilicon film 11 serving as a second capacitor
electrode is filled in the trench 23 such that it contacts the SiO.sub.2
/SiN film 10 and also the drain region 18.
FIGS. 8-10 are views, useful in explaining essential steps of a method for
forming the structure shown in FIG. 7. Elements similar to those in the
first embodiment are denoted by corresponding reference numerals. As is
shown in FIG. 8, a trench 23 having a depth of 5 .mu.m is formed in the
p-type surface of a monocrystal silicon substrate 21. Then, a polysilicon
film 5 having a thickness of 60 nm, a SiN film 6 having a thickness of 12
nm and a SiO.sub.2 film 7 having a thickness of 50 nm are deposited by the
CVD method in this order. Subsequently, an exposed portion of the
SiO.sub.2 film 7 is removed by a buffer HF aqueous solution, using as a
mask a resist layer 8 having a thickness of 3 .mu.m and formed on the
bottom of the trench.
Then, as is shown in FIG. 9, the resist layer 8 is removed, and an exposed
portion of a SiN film 6 is removed by a hot H.sub.3 PO.sub.4 aqueous
solution, using as a mask the SiO.sub.2 film 7. Subsequently, the
SiO.sub.2 film 7 is removed by the buffer HF aqueous solution. At this
time, only that portion of the SiN film 6 having been located under the
SiO.sub.2 film remains. Then, that exposed portion of the polysilicon film
5 on which the SiN film 6 does not remain is oxidized by thermal
oxidation, thereby forming a SiO.sub.2 film 9 with a thickness of 50 nm.
The SiN film 6 is removed by the hot H.sub.3 PO.sub.4 aqueous solution.
The polysilicon film 5 may be doped with phosphorus or arsenic of high
density in this stage. Phosphorus or arsenic is diffused from the
polysilicon film 5 to the outside of the trench, thereby forming a
diffusion layer 27.
Then, as is shown in FIG. 10, a SiN film (10) having a thickness of 10 nm
is deposited by the CVD method, and a thin surface portion thereof is
oxidized by high temperature oxidation, thereby forming a capacitor
insulating film 10 of high quality. Alternatively, the SiN film 6 may not
be removed after forming the SiO.sub.2 film 9, and used as the capacitor
insulating film. Subsequently, a polysilicon film 11 having a thickness of
400 nm is formed in the trench by the low pressure CVD method such that it
almost completely fills the trench. As in the case of the polysilicon film
5, phosphorus is injected into the polysilicon film 11. Thereafter, the
polysilicon film 11 is selectively etched back by isotropic dry etching to
have a thickness of 4.5 .mu.m from the bottom of the trench. Then, a
surface portion of the polysilicon film 11 is oxidized by high temperature
oxidation, thereby forming a SiO.sub.2 film 12 with a thickness of 10 nm.
Thereafter, a memory cell of the DRAM shown in FIG. 7 is formed in a
process similar to that employed in the first embodiment. Specifically,
the trench is filled with a polysilicon film 14, a surface portion of the
polysilicon film 14 is oxidized (thereby forming a SiO.sub.2 film 15), a
gate electrode 19 is selectively formed on the SiO.sub.2 film 2, and
source/drain regions 18 are formed such that one of the regions 18
contacts the diffusion layer 16.
FIG. 12 is a cross sectional view, showing essential part of a sheath-plate
type trench capacitor employed in a DRAM according to a third embodiment
of the invention. FIG. 11 is a cross sectional view, showing a step for
obtaining the structure shown in FIG. 12. Elements similar to those
employed in the first or second embodiment are denoted by corresponding
reference numerals. Referring to FIG. 11, a trench with a depth of 5 .mu.m
and a diameter of 0.5 .mu.m is formed in the p-type surface of a
monocrystal silicon substrate 21. Then, a SiN film 6 with a thickness of
12 nm and a SiO.sub.2 film 7 with a thickness of 50 nm are deposited in
this order by the CVD method. Subsequently, the SiO.sub.2 film 7 is
removed by a buffer HF aqueous solution, using as a mask a resist layer 8
having a thickness of 3 .mu.m and formed on the bottom of the trench.
Then, as is shown in FIG. 12, the resist layer 8 is removed, and an exposed
portion of the SiN film 6 is removed by a hot H.sub.3 PO.sub.4 aqueous
solution, using as a mask the SiO.sub.2 film 7. Subsequently, the
SiO.sub.2 film 7 is removed by a buffer HF aqueous solution. Then, that
portion of the silicon substrate which has been exposed after removing the
SiN film 6 is subjected to high temperature oxidation, thereby forming a
SiO.sub.2 film 9 having a thickness of 50 nm. The SiO.sub.2 film 6 is then
removed by the hot H.sub.3 PO.sub.4 aqueous solution. Subsequently, an
exposed portion of the substrate in the trench is doped with phosphorus or
arsenic of high density to form a diffusion layer 27. Thereafter, as in
the case of FIG. 10, a SiN film (10) with a thickness of 10 nm is
deposited by the CVD method, a shallow surface portion thereof is
oxidized, thereby obtaining capacitor insulating film 10 of high quality.
Thereafter, a memory cell of the DRAM can be formed in a process similar
to that employed in the first or second embodiment.
FIG. 14 is a cross sectional view, showing essential part of a sheath-plate
type trench capacitor employed in a DRAM according to a fourth embodiment
of the invention, while FIG. 13 is a cross sectional view, showing a step
for obtaining the structure shown in FIG. 14. Elements similar to those
employed in the first embodiment are denoted by corresponding reference
numerals. Referring to FIG. 13, a trench with a depth of 5 .mu.m and a
diameter of 0.5 .mu.m is formed in the p-type surface of a monocrystal
silicon substrate 21. Then, a polysilicon film 5 with a thickness of 60 nm
and a SiN film 6 with a thickness of 12 nm are deposited in this order by
the CVD method. The polysilicon film 5 is doped with phosphorus or arsenic
of high quality while or after it is formed. Phosphorus or arsenic
injected in the film 5 diffuses into the substrate in a heating step
performed later. Subsequently, a shallow surface portion of the SiN film 6
is oxidized, and a polysilicon film 11 with a thickness of 400 nm is
deposited in the trench by the CVD method. Then, the polysilicon film 11
is selectively etched back by isotropic dry etching to have a thickness of
3 .mu.m from the bottom of the trench, and en exposed portion of the SiN
film 6 is removed by the use of a hot H.sub.3 PO.sub.4 aqueous solution.
Subsequently, as is shown in FIG. 14, an exposed portion of the polysilicon
film 5 is completely oxidized by high temperature oxidation, forming a
SiO.sub.2 film 9. At the same time as the oxidation of the polysilicon
film 5, part of the substrate may be oxidized. An upper surface portion of
the polysilicon film 11 is oxidized, thereby forming a SiO.sub.2 film 12
(not shown). Then, that portion of the SiO.sub.2 film 9 which extends to
the upper surface of the polysilicon film 11 is removed by unisotropic
etching. The SiO.sub.2 film 12 is removed together with the SiO.sub.2 film
9. Thereafter, a memory cell of the DRAM can be formed in the same process
as employed in the second embodiment.
The second through fourth embodiments can provide the same advantage as
obtained by the first embodiment. That is, in the sheath-plate type trench
capacitor structure, the portion of an oxide film which extends from an
upper edge portion of a capacitor electrode formed on the trench inner
wall to the conductive region (drain region 18) of the transistor is
formed thick such that it projects inward of the trench, so as to prevent
that portion from changing to an inversion layer. Therefore, a junction
leak current can be reduced without reducing a substantial area of the
capacitor located below that portion.
In the above embodiments, the monocrystal silicon semiconductor substrate
21 may be a p-type well region 211 formed on an n-type substrate 212 as
shown, for example, in FIG. 15 corresponding to FIG. 2 or FIG. 16
corresponding to FIG. 7; or may be a p-type region 211 formed on a p-type
substrate 213 as shown, for example, in FIG. 17 corresponding to FIG. 2 or
FIG. 18 corresponding to FIG. 7. In the latter case shown in FIG. 17, an
n-type region 31 for supplying a potential and connecting another trench
(not shown) is provided in the p-type substrate 213 such that it contacts
the polysilicon film 5 serving as a first capacitor electrode. The
diffusion layer 27 as shown in FIGS. 7, 12 and 18 has the same function as
the n-type region 31 mentioned above. The n-type region 31 may be a
diffusion layer formed by diffusing an impurity from the bottom of the
trench to the substrate, or may be a diffusion layer beforehand embedded
in the substrate.
Additional advantages and modifications will readily occur to those skilled
in the art. Therefore, the invention in its broader aspects is not limited
to the specific details, representative devices, and illustrated examples
shown and described herein. Accordingly, various modifications may be made
without departing from the spirit or scope of the general inventive
concept as defined by the appended claims and their equivalents.
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