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United States Patent | 6,073,254 |
Whetsel | June 6, 2000 |
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
Inventors: | Whetsel; Lee D. (Allen, TX) |
Assignee: | Texas Instruments Incorporated (Dallas, TX) |
Appl. No.: | 918872 |
Filed: | August 26, 1997 |
Current U.S. Class: | 714/30; 714/727; 714/729 |
Intern'l Class: | G06F 011/00 |
Field of Search: | 713/600 714/30,25,48,726,727,729 371/22.3 709/9 |
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Foreign Patent Documents | |||
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Breuer M. A. et al., A Test and Maintenance Controller for a Module Containing Testable Chip, 1988 International Test Conference, Sep. 12, 1988, pp. 502-513, 1988 IEEEs. Maunder, C., A Universal Framework for Managed Built-In Test, International Test Conference 1993, Jan. 1, 1993, pp. 21-29, 1993 IEEE. "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Computer Society, Oct. 21, 1993. "SCANPSC110F SCAN.TM. Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE 1149.1 System Test Support)," National Semiconductor, Sep. 1993, pp. 1-32. "SN54ACT8999, SN74ACT8999 Scan Path Selectors with 8-Bit Bidirectional Data Buses," Texas Instruments Product Review, Jun. 1990, pp. 11-166 to 11-194. |