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United States Patent | 6,051,864 |
Hodges ,   et al. | April 18, 2000 |
An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.
Inventors: | Hodges; Robert Louis (Lewisville, TX); Nguyen; Loi Ngoc (Carrollton, TX) |
Assignee: | STMicroelectronics, Inc. (Carrollton, TX) |
Appl. No.: | 890636 |
Filed: | July 14, 1997 |
Current U.S. Class: | 257/384; 257/296; 257/369; 257/754; 257/E21.507; 257/E21.575; 257/E27.081 |
Intern'l Class: | H01L 029/78; H01L 029/45 |
Field of Search: | 257/296,369,754,384 |
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