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United States Patent | 6,051,507 |
Jenq ,   et al. | April 18, 2000 |
The invention provides a method of fabricating a capacitor with high capacitance. A substrate having word lines and bit lines is provided, and a dielectric layer is formed to cover the substrate. A contact window is formed in the dielectric layer to expose an active region. A conductive layer is formed to fill the contact window to connect with the active region. An insulating layer is formed on the conductive layer and the insulating layer and the conductive layer are defined. A hemispherical grained-Si (HSG-Si) layer is then formed on the substrate. An etching process is performed on the HSG-Si layer to expose the dielectric layer using a portion of the insulating layer as a mask. The insulating layer is removed. A storage node with a gear toothed profile is then formed.
Inventors: | Jenq; J. S. Jason (Pingtung, TW); Wu; Der-Yuan (Hsinchu, TW) |
Assignee: | United Microelectronics Corp. (Hsinchu, TW) |
Appl. No.: | 172406 |
Filed: | October 14, 1998 |
Aug 04, 1998[TW] | 87112805 |
Current U.S. Class: | 438/719; 257/E21.012; 438/738; 438/756 |
Intern'l Class: | H01L 021/00 |
Field of Search: | 438/691,706,710,719,723,725,738,743,756 216/38.51,67,79,88,99 |
5464791 | Nov., 1995 | Hirota | 438/754. |
5928969 | Jul., 1999 | Li et al. | 438/753. |