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United States Patent | 6,048,757 |
Takemura | April 11, 2000 |
A thin film transistor of reversed stagger type having improved characteristics and yet obtained by a simple process, which is fabricated by selectively doping the semiconductor region on the gate dielectric to form the source, drain, and channel forming regions by using ion implantation, ion doping, or doping a plasma of ions; and then effecting rapid thermal annealing by irradiating a ultraviolet radiation, a visible light, or a near-infrared radiation for a short period of time. The source, drain, and channel forming regions are formed substantially within a single plane.
Inventors: | Takemura; Yasuhiko (Kanagawa, JP) |
Assignee: | Semiconductor Energy Laboratory Co., Ltd. (Kanagawa, JP) |
Appl. No.: | 942440 |
Filed: | October 1, 1997 |
Aug 12, 1993[JP] | 5-220594 |
Intern'l Class: | H01L 021/84 |
Field of Search: | 438/151,166,308,795,158-160 |
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