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United States Patent | 6,031,410 |
Kanno | February 29, 2000 |
In a multiplexor, respective outputs of two latches alternately brought into a dynamic holding condition at phases opposite to each other, respectively, are connected in common in a wired connection. Thus, a selector becomes unnecessary, with the result that the number of transistors driven with a clock signal can be reduced, and the electric power consumption is correspondingly reduced.
Inventors: | Kanno; Hiroshi (Tokyo, JP) |
Assignee: | NEC Corporation (Tokyo, JP) |
Appl. No.: | 058964 |
Filed: | April 13, 1998 |
Apr 11, 1997[JP] | 9-110326 |
Current U.S. Class: | 327/407; 327/99; 327/200; 365/189.02; 365/189.05 |
Intern'l Class: | H03K 017/62; H03K 003/037 |
Field of Search: | 327/200,407,99,201,408,409 365/189.02,189.05 |
5254888 | Oct., 1993 | Lee et al. | 327/152. |
5576651 | Nov., 1996 | Phillips | 327/202. |
5619157 | Apr., 1997 | Kumata et al. | 327/203. |
5646555 | Jul., 1997 | Morinaka | 327/201. |
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