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United States Patent | 6,031,289 |
Fulford, Jr. ,   et al. | February 29, 2000 |
An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
Inventors: | Fulford, Jr.; H. Jim (Austin, TX); Bandyopadhyay; Basab (Austin, TX); Dawson; Robert (Austin, TX); Hause; Fred N. (Austin, TX); Michael; Mark W. (Cedar Park, TX); Brennan; William S. (Austin, TX) |
Assignee: | Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Appl. No.: | 034589 |
Filed: | March 4, 1998 |
Current U.S. Class: | 257/758; 257/776; 257/E21.575; 257/E23.144 |
Intern'l Class: | A07C 029/41 |
Field of Search: | 257/758,759,760,773,774,775,776 |
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