Back to EveryPatent.com
United States Patent | 6,012,134 |
McInerney ,   et al. | January 4, 2000 |
A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers in a first pipeline stage, which is used to produce a physical address from an ITLB lookup. A comparison is performed by compare logic between the physical address (and tags) of a set in the local cache and the set associated with the selected instruction pointer. A way multiplexer selects the proper way output from either the compare logic or an instruction streaming buffer that stores instructions returned from the first cache, but not yet written into the local cache. An instruction is bypassed to the way multiplexer from the instruction streaming buffer in response to an instruction streaming buffer hit and a miss signal by the compare logic.
Inventors: | McInerney; Rory (Sunnyvale, CA); Sindelar; Eric (Sunnyvale, CA); Yeh; Tse-Yu (Milpitas, CA); Ramakrishnan; Kalpana (Belmont, CA) |
Assignee: | Institute for the Development of Emerging Architectures, L.L.C. (Cupertino, CA) |
Appl. No.: | 057968 |
Filed: | April 9, 1998 |
Current U.S. Class: | 711/207; 711/141; 711/205; 712/210; 712/211 |
Intern'l Class: | G06F 009/34; G06F 009/38 |
Field of Search: | 711/205,140,118,3,154,141,130,137,207,204,117 712/210,207,215,233,235,239,211,219 713/322 |
5148536 | Sep., 1992 | Witek et al. | 711/140. |
5553255 | Sep., 1996 | Jain et al. | 712/235. |
5586295 | Dec., 1996 | Tran | 711/137. |
5590294 | Dec., 1996 | Mirapuri et al. | 712/244. |
5592679 | Jan., 1997 | Yung | 711/117. |
5606675 | Feb., 1997 | Sakamura et al. | 712/237. |
5634103 | May., 1997 | Dietz et al. | 712/235. |
5634131 | May., 1997 | Matter et al. | 713/322. |
5642500 | Jun., 1997 | Inoue | 712/233. |