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United States Patent | 6,009,503 |
Liedtke | December 28, 1999 |
The memory device comprises a cache memory indexed by the cache index and group information of the virtual address. The physical address translated from the virtual address contains primary and secondary group information. If the tag of the cache entry addressed according to the above standard by indexing of the cache memory corresponds to the physical address, indexing is carried out again using the second group information associated with the physical address (and using the cache index of the virtual address). If the tag of the cache entry thus addressed still does not correspond to the physical address, a cache miss is signaled.
Inventors: | Liedtke; Jochen (Sankt Augustin, DE) |
Assignee: | International Business Machines Corporation (Armonk, NY) |
Appl. No.: | 732352 |
Filed: | October 29, 1996 |
PCT Filed: | April 19, 1995 |
PCT NO: | PCT/EP95/01471 |
371 Date: | October 29, 1996 |
102(e) Date: | October 29, 1996 |
PCT PUB.NO.: | WO95/29445 |
PCT PUB. Date: | November 2, 1995 |
Apr 22, 1994[DE] | 44 14 116 | |
May 11, 1994[DE] | 44 16 562 | |
Feb 10, 1995[DE] | 195 04 483 |
Current U.S. Class: | 711/203; 711/200; 711/202; 711/220 |
Intern'l Class: | G06F 012/00 |
Field of Search: | 711/3,6,118,100,200,202,203,206,216,220,221,1,5,108,117,147,210 |
5226133 | Jul., 1993 | Taylor et al. | 395/400. |
5752069 | May., 1998 | Roberts et al. | 711/204. |
5761726 | Jun., 1995 | Guttag et al. | 711/147. |
Foreign Patent Documents | |||
WO 88/09014 | Nov., 1988 | WO. |
Patterson and Hennessy, "Computer Architecture A Quantitative Approach", pp. 432-448, Dec. 1990. |