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United States Patent | 5,794,017 |
Evans ,   et al. | August 11, 1998 |
The graphics display system comprises a data bus for transferring a set of application pixels, wherein a set consists of W number of blocks of data, and wherein each application pixel is M number of blocks. The graphics display system further comprises an address bus for transferring memory addresses, a graphics controller for outputting pixel data on the data bus at a rate of one set per memory clock cycle and for outputting one or more column addresses on the address bus for each set, and a graphics memory configured for a memory field size of N number of blocks such that an application pixel being stored is allocated N blocks. A set of application pixels is transferred over the data bus to the graphics memory, and, one or more column addresses are transferred over the address bus during the a memory clock cycle over the address bus. In addition, a row address is transferred to the graphics memory. Each block of the transferred set belongs to one of N/M groups of blocks, and each of these blocks are stored in the graphics memory in a memory field indicated by a transferred row and column address pair, wherein each group of blocks is stored at a different one of N/M number of column addresses for any given transferred set.
Inventors: | Evans; Edward Kelley (Essex Junction, VT); Liguori; Daniel Joseph (Essex Junction, VT); West; Roderick Michael Peters (Colchester, VT) |
Assignee: | International Business Machines Corporation (Armonk, NY) |
Appl. No.: | 384077 |
Filed: | February 6, 1995 |
Current U.S. Class: | 345/544; 345/213; 345/501; 345/531 |
Intern'l Class: | G06T 001/60 |
Field of Search: | 395/162-166,140-141,526,507,501,509,515,517 345/24,27-28,133,185-187,189-190,200,201,213 |
5398316 | Mar., 1995 | Guttag et al. | 395/164. |