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United States Patent | 5,749,094 |
Jaggar | May 5, 1998 |
A data processing system is described having a central processing unit (CPU) 4, a memory management unit (MMU) 6 and a cache memory 8. The CPU 4 makes cache writes in the same clock cycle that the data is output from the CPU 4. In a following clock cycle, the MMU 6 produces a signal IC indicating whether that storage operation was invalid. If the storage operation was invalid, then a flag associated with a cache storage line storing a plurality of output data words is set to indicate such invalid storage.
Inventors: | Jaggar; David Vivian (Cherry Hinton, GB) |
Assignee: | Advanced Risc Machines Limited (Cambridge, GB) |
Appl. No.: | 747196 |
Filed: | November 12, 1996 |
Sep 29, 1993[GB] | 9320143 |
Current U.S. Class: | 711/139; 711/135 |
Intern'l Class: | G06F 012/12 |
Field of Search: | 395/466,468,471,473,462 711/135,139,141,144,146,145,143 |
5226133 | Jul., 1993 | Taylor et al. | 711/207. |
5325499 | Jun., 1994 | Kummer et al. | 711/143. |
5408636 | Apr., 1995 | Santeler et al. | 711/163. |
Foreign Patent Documents | |||
0 210 384 A1 | Feb., 1987 | EP. |
Intel, "Intel DX4 Processor Data Book," Feb. 1994, pp. 8-22 & 8-24, 6-1 to 6-2. Fu et al., "Performance and Microarchitecture of the i486.TM. Processor", 1989, IEEE, pp. 182-187. Miyake et al., "A 40 MIPS (Peak) 64-bit Microprocessor with One-Clock Physical Cache Load/Store", 1990, IEEE, pp. 42-43, 261. Safai, M., and Stodieck, R., "Complete High-Performance Cache System for the 80386", Microprocessors and Microsystems, vol. 14, No. 10, Dec. 1990, pp. 664-674. |