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United States Patent | 5,740,096 |
Shou ,   et al. | April 14, 1998 |
The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.
Inventors: | Shou; Guoliang (Tokyo, JP); Zhou; Changming (Tokyo, JP); Yamamoto; Makoto (Tokyo, JP); Sawahashi; Mamoru (Kanagawa, JP); Adachi; Fumiyuki (Kanagawa, JP); Takatori; Sunao (Tokyo, JP) |
Assignee: | NTT Mobile Communications Network, Inc. (Tokyo, JP); Yozan, Inc. (Tokyo, JP) |
Appl. No.: | 708986 |
Filed: | September 6, 1996 |
Sep 08, 1995[JP] | 7-255758 |
Current U.S. Class: | 708/819 |
Intern'l Class: | G06G 007/02 |
Field of Search: | 364/825,724.11,717 |
4507746 | Mar., 1985 | Fletcher, Jr. |
Povey et al., "Simplified Matched Filter Receiver Designs for Spread Spectrum Communications Applications", Electronics & Communication Engineering Journal, vol. 5, No. 2, Apr. 1, 1993. Nauerz, "The Suitability of Modern CMOS Gate Array Circuits as Correlations and Matched Filters for Spread-Spectrum Signals", Crisis Communications, vol. 2 of 3, Oct. 1987. Tanaka et al., Development of Low Power Consumption LSI for SS Communication, Technical Report of IEICE, SST95-77, Oct. 1995. Ogawa et al., Development of 1 Chip SS Communication LSI Using Digital Matched Filters, Technical Report of IEICE, ISEC94-42, SST94-65, Dec. 1994. Dual 64-TAP, 11 Mcps Digital Matched Filter/Correlator STEL-3310, Stanford Communications, 1990. Tachika et al., A Development Conditions and Its Technical Issue of Digital Matched Filters in Spread-Spectrum Communication Systems, Technical Report of IEICE, SST92-21, 1992. |
TABLE 1 ______________________________________ CAPACITIVE COUPLING CAPACITANCE CAPACITY ______________________________________ CP84 C841 16Cu C842 8Cu C843 4Cu C844 2Cu C845 Cu C846 Cu CP83 C831 16Cu C832 8Cu C833 4Cu C834 2Cu C835 2Cu CP82 C821 16Cu C822 8Cu C823 4Cu C824 4Cu CP81 C811 16Cu C812 8Cu C813 8Cu ______________________________________
TABLE 2 ______________________________________ INPUT INNER INTERMEDIATE VOLTAGE OUTPUT OUTPUT ______________________________________ Vi8 b3' b2' b1' b0' b3 b2 b1 b0 0 .ltoreq. Vi8 < Vdd Vdd Vdd Vdd 0 0 0 0 Va Va .ltoreq. Vi8 < 0 Vdd Vdd Vdd Vdd 0 0 0 2Va 2Va .ltoreq. Vi8 < Vdd 0 Vdd Vdd 0 Vdd 0 0 3Va 3Va .ltoreq. Vi8 < 0 0 Vdd Vdd Vdd Vdd 0 0 4Va 4Va .ltoreq. Vi8 < Vdd Vdd 0 Vdd 0 0 Vdd 0 5Va 5Va .ltoreq. Vi8 < 0 Vdd 0 Vdd Vdd 0 Vdd 0 6Va 6Va .ltoreq. Vi8 < Vdd 0 0 Vdd 0 Vdd Vdd 0 7Va 7Va .ltoreq. Vi8 < 0 0 0 Vdd Vdd Vdd Vdd 0 8Va 8Va .ltoreq. Vi8 < Vdd Vdd Vdd 0 0 0 0 Vdd 9Va 9Va .ltoreq. Vi8 < 0 Vdd Vdd 0 Vdd 0 0 Vdd 10Va 10Va .ltoreq. Vi8 < Vdd 0 Vdd 0 0 Vdd 0 Vdd 11Va 11Va .ltoreq. Vi8 < 0 0 Vdd 0 Vdd Vdd 0 Vdd 12Va 12Va .ltoreq. Vi8 < Vdd Vdd 0 0 0 0 Vdd Vdd 13Va 13Va .ltoreq. Vi8 < 0 Vdd 0 0 Vdd 0 Vdd Vdd 14Va 14Va .ltoreq. Vi8 < Vdd 0 0 0 0 Vdd Vdd Vdd 15Va 15Va .ltoreq. Vi8 < 0 0 0 0 Vdd Vdd Vdd Vdd 16Va ______________________________________