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United States Patent | 5,736,438 |
Nishimura ,   et al. | April 7, 1998 |
In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.
Inventors: | Nishimura; Hisayuki (Hyogo, JP); Sugahara; Kazuyuki (Hyogo, JP); Maeda; Shigenobu (Hyogo, JP); Ipposhi; Takashi (Hyogo, JP); Inoue; Yasuo (Hyogo, JP); Iwamatsu; Toshiaki (Hyogo, JP); Ikeda; Mikio (Hyogo, JP); Kunikiyo; Tatsuya (Hyogo, JP); Tateishi; Junji (Hyogo, JP); Minato; Tadaharu (Hyogo, JP) |
Assignee: | Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP); Ryoden Semiconductor System Engineering Corporation (Hyogo, JP) |
Appl. No.: | 483411 |
Filed: | June 7, 1995 |
Oct 28, 1992[JP] | 4-290293 |
Current U.S. Class: | 438/166; 257/E21.661; 257/E27.1; 257/E29.286; 438/162 |
Intern'l Class: | H01L 021/84 |
Field of Search: | 437/21,24,83,101,233,40 TFT,41 TFT 117/7,8,9 438/166,162 |
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__________________________________________________________________________ Current Value Channel Region per 1 .mu.m Method Of No. Of Density of Channel Width Manufacturing TFT Grain Boundary Crystal Defects ON OFF No. Active Layer (pieces) (pieces/cm.sup.2) (.mu.A) (1A) Determination __________________________________________________________________________ 1 B 0 1 .times. 10.sup.8 2 6 .largecircle. 2 A, E 0 5 .times. 10.sup.8 0.25 15 .largecircle. 3 C, D, E, F, G, H 0 2 .times. 10.sup.8 1 10 .largecircle. 4 Conventional Solid 0 1 .times. 10.sup.9 0.2 30 X Phase Growth 5 Conventional Solid 1 1 .times. 10.sup.9 0.1 40 X Phase Growth 6 Laser Annealing 1 1 .times. 10.sup.5 4 10 .largecircle. (Large Output) 7 Laser Annealing .sup..about. 10 1 .times. 10.sup.9 2 pA 40 X (Small Output) 8 LPCV Method .sup..about. 100 .sup. 1 .times. 10.sup.12 50 pA 40 X ((Polycrystalline Layer of Minute Grain Size) __________________________________________________________________________