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United States Patent | 5,725,658 |
Sawada | March 10, 1998 |
When a film is formed on a wafer of groups III-V compound semiconductors by heating, slips are formed in the periphery of the wafer because of residual inner stress of the wafer. The quality of an epitaxially grown crystal is damaged by these slips. The residual stress of the wafer is caused by the residual stress generated in an inner part of an ingot at the time of growing a crystal. Therefore, it is an object to prepare a wafer in which no slips are generated when the epitaxial growth is carried out. In order to achieve this object, a method is provided in which; an ingot is heated and cooled in a range between an upper limit temperature T.sub.h, and a lower limit temperature T.sub.1 where the upper limit temperature ranges from more than 800.degree. C. to less than a melting point of a material of the ingot, and the lower limit temperature ranges from more than 800.degree. C. to less than the upper limit temperature T.sub.h. The reciprocating changing between of heating and cooling steps is repeated a plurality of times at a speed A of raising temperature and a speed B of lowering temperature where the speed A of raising temperature is lower than the speed B of lowering temperature. The residual stress is excluded by this heat-treatment method, and, consequently, no slips occur in the peripheral part of a wafer obtained by this invention.
Inventors: | Sawada; Shin-ichi (Osaka, JP) |
Assignee: | Sumitomo Electric Industries, Ltd. (Osaka, JP) |
Appl. No.: | 417773 |
Filed: | April 6, 1995 |
Oct 24, 1994[JP] | 6-284285 |
Current U.S. Class: | 117/54; 117/56 |
Intern'l Class: | C30B 019/10 |
Field of Search: | 117/54,56,57,61,81,82,83 |
Foreign Patent Documents | |||
1242498 | Mar., 1988 | JP. | |
517097 | Sep., 1991 | JP. |
Chemical Abstracts, vol. 113, No. 12, 1990, Sep. 17, Columbus, Ohio, USA Yamamoto M. et al., "Manufacture of compound semiconductor wafers", p. 711. Chemical Abstracts, vol. 119, No. 6, 1993, Aug. 9, Columbus, Ohio, USA, Inada T. et al., "Manufacture of gallium arsenide single crystal wafer by ion implantation", p. 851. "Development of High Quality 4-inch Semi-Insulating GaAs Crystal Wafers", M. Kashiwa, et al, Hitachi Cable Review No. 9, p. 55 (Aug., 1990). |