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United States Patent | 5,719,439 |
Iwasaki ,   et al. | February 17, 1998 |
A semiconductor chip having a semiconductor substrate, a plurality of pads formed above the semiconductor substrate a first passivating film formed over an entire surface of the semiconductor substrate, and having openings above the pads the surface of the first passivating film being flat, a plurality of interconnection lines formed on the surface of the first passivating film, a second passivating film formed over the entire surface of the first passivating film and having through holes, the through holes being arranged in the form of an array, the surface of the second passivating film being flat, a plurality of contacts for connection to external leads each of the contacts being formed within and above a respective one of the through holes, the contacts being arranged in the form of an array.
Inventors: | Iwasaki; Hiroshi (Yokohama, JP); Aoki; Hideo (Yokohama, JP) |
Assignee: | Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Appl. No.: | 537396 |
Filed: | October 2, 1995 |
Oct 03, 1994[JP] | 6-239042 | |
Aug 30, 1995[JP] | 7-221827 |
Intern'l Class: | H01L 023/528 |
Field of Search: | 257/690,697,700,701,702,737,738,750,758,760,762,773,777,778,780,786,764,766 |
4107726 | Aug., 1978 | Schilling | 257/766. |
5220199 | Jun., 1993 | Owada et al. | 257/758. |
5309024 | May., 1994 | Hirano | 257/697. |
5360988 | Nov., 1994 | Uda et al. | 257/666. |
5457345 | Oct., 1995 | Cook et al. | 257/766. |
5581122 | Dec., 1996 | Chao et al. | 257/738. |