Back to EveryPatent.com
United States Patent | 5,696,943 |
Lee | December 9, 1997 |
In order to reduce product's time to market, a designer has to plan for debugging silicon before the first tape out. Having the proper type of spare gates at the desirable location will limit the number of new masks to three if not just one. Moreover, when these spare gates are easy to locate and are in the proper format, a FIB system can be used to debug the silicon and test the new fixes in real system environment before the next tape out. Thus, the spare gate strategy can limit the iteration of mask changes to just one, and this will speed up the time to market and bring higher profit from the product.
Inventors: | Lee; Dennis (San Jose, CA) |
Assignee: | Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Appl. No.: | 508200 |
Filed: | July 27, 1995 |
Current U.S. Class: | 716/4; 716/5 |
Intern'l Class: | G06F 017/50 |
Field of Search: | 395/500 29/571 365/200 307/202.1 364/490,488,489 371/5.5,10.1 326/39,49,55 257/685 |
4319396 | Mar., 1982 | Law et al. | 29/571. |
4471472 | Sep., 1984 | Young | 365/200. |
4485459 | Nov., 1984 | Venkateswaran | 365/200. |
4494220 | Jan., 1985 | Dumbri et al. | 365/200. |
4590388 | May., 1986 | Clemons et al. | 307/202. |
4931946 | Jun., 1990 | Ravindra et al. | 364/490. |
5157618 | Oct., 1992 | Ravindra et al. | 364/490. |
5337318 | Aug., 1994 | Tsukakoshi et al. | 371/5. |
5416740 | May., 1995 | Fujita et al. | 365/200. |
5426379 | Jun., 1995 | Trimberger | 326/39. |
5434868 | Jul., 1995 | Aichelmann, Jr. et al. | 371/10. |
5502333 | Mar., 1996 | Bertin et al. | 257/685. |
5568067 | Oct., 1996 | McDermott et al. | 326/55. |
5592107 | Jan., 1997 | McDermott et al. | 326/49. |
"Fault Trees and Sequence Dependencies", by J. Dugan et al., IEEE, Reliability & Maintainability, 1990 Symposium, pp. 286-293. "A Parallel Algorithm for Allocation of Spare Cells on Memory Chips", by N. Funabiki et al., IEEE Transactions on Reliability, vol. 40, No. 3, Aug. 1991, pp. 338-346. "Design and Analysis of Defect Tolerant Hierarchical Sorting Networks", by S. Kuo et al., IEEE, Wafer Scale Integration, 1992 International Conference, May 1992, pp. 240-249. "Restructuring WSI Hexagonal Processor Arrays", by R. Venkateswaran et al., IEEE Transactions on Computer-Aided Design, vol. 11, No. 12, Dec. 1992, pp. 1574-1585. "Faust: A Fault Tolerant Sparing Technique for ATM Switch Architectures", by K. Padmanabhan, Globecom '93: IEEE Global Telecommunications Conference, 1993, pp. 1368-1374. "An Efficient Architecture for Fault-Tolerant ATM Switches", by K. Padmanabhan, IEEE/ACM Transactions on Networking, vol. 3, No. 5, Oct. 1995, pp. 527-537. |