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United States Patent | 5,667,940 |
Hsue ,   et al. | September 16, 1997 |
A new photolithographic process using the method of photoresist double coating to fabricate fine lines with narrow spacing is described. A layer to be etched is provided overlying a semiconductor substrate. The layer to be etched is coated with a first layer of photoresist and baked. The first photoresist layer is exposed to actinic light through openings in a mask and developed to produce the desired first pattern on the surface of the first photoresist wherein the openings have a minimum width of the resolution limit plus two times the misalignment tolerance of the photolithography process. The layer to be etched is coated with a second photoresist layer where the layer to be etched is exposed within the openings in the first photoresist layer. The second photoresist layer is exposed to actinic light through openings in a mask and developed to produce the desired second pattern on the surface of the second photoresist wherein the second pattern alternates with the first photoresist pattern and wherein the spacing between the first and second patterned photoresist coatings has a width equal to the misalignment tolerance. The misalignment tolerance is much smaller than the resolution limit so the line spacing achieved is narrower than the resolution limit of the photolithography process.
Inventors: | Hsue; Chen-Chiu (Hsin-Chu, TW); Hong; Gary (Hsin-Chu, TW) |
Assignee: | United Microelectronics Corporation (Hsin-Chu, TW) |
Appl. No.: | 746147 |
Filed: | November 6, 1996 |
Current U.S. Class: | 430/312; 257/E21.024; 257/E21.027; 257/E21.314; 430/313; 430/314; 430/328; 430/330; 430/394 |
Intern'l Class: | G03F 007/26 |
Field of Search: | 430/312,313,314,328,330,394 |
4591547 | May., 1986 | Brownell | 430/312. |
4704347 | Nov., 1987 | Vollenbroek et al. | 430/312. |
4906552 | Mar., 1990 | Ngo et al. | 430/312. |
5091290 | Feb., 1992 | Rolfson | 430/327. |