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United States Patent | 5,661,056 |
Takeuchi | August 26, 1997 |
A tunnel oxide film is formed on the surface of a p-type silicon substrate, and a floating gate electrode made from a polysilicon film is formed on the surface of the tunnel oxide film. On the surface of the floating gate electrode, a control gate electrode is formed via an NON film formed by sequentially stacking a silicon nitride film, a silicon oxide film, and a silicon nitride film. A side oxide film is formed on the side surfaces of the floating gate electrode and the control gate electrode. Source and drain regions made from an n-type diffused layer are formed on the surfaces of element regions of the silicon substrate on the two sides of the floating gate electrodes.
Inventors: | Takeuchi; Nobuyoshi (Tokyo, JP) |
Assignee: | NKK Corporation (Tokyo, JP); Macronix International Co., Ltd. (Hsinchu, TW) |
Appl. No.: | 533169 |
Filed: | September 25, 1995 |
Sep 29, 1994[JP] | 6-259009 | |
Sep 18, 1995[JP] | 7-237959 |
Current U.S. Class: | 438/261; 257/E21.68; 257/E27.103; 257/E29.129; 257/E29.165; 438/591; 438/954 |
Intern'l Class: | H01L 021/824.7 |
Field of Search: | 437/43,52,978 |
5045488 | Sep., 1991 | Yeh | 437/43. |
5158902 | Oct., 1992 | Hanada | 437/43. |
5445981 | Aug., 1995 | Lee | 437/43. |
5460992 | Oct., 1995 | Hasegawa | 437/43. |
5470771 | Nov., 1995 | Fujii et al. | 437/43. |
Foreign Patent Documents | |||
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3-57279 | Mar., 1991 | JP. | |
5-267684 | Mar., 1992 | JP. | |
6-90008 | May., 1992 | JP. | |
6-77493 | Aug., 1992 | JP. | |
6-77497 | Aug., 1992 | JP. |
C. S. Lai et al., "The Electrical characteristics of Polysilicon Oxide Grown in Pure N.sub.2 O", IEEE Electron Device Letters, vol. 16, No. 9, Sep. 1995. S. Chiang et al; "Antifuse Structure Comparison for Field Programmable Gate Arrays", IEDM 92, pp. 611-614, 1992, month unknown. Y. Okada et al., "Furnace Grown Gate Oxcynitride Using Nitric Oxide (NO)", IEEE Transactions on Electron Devices, vol. 41, No. 9, Sep. 1994. S. Mori et al., "Bottom-Oxide Scaling for Thin Nitride/Oxide Interpoly Dielectric in Stacked-Gate Nonvolatile Memory Cells", IEEE Transactions on Electron Devices, vol. 39, No. 2., Feb. 1992. |