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United States Patent | 5,644,600 |
Kawai | July 1, 1997 |
A multi-valued signal decoding circuit is disclosed which has a circuit for detecting a bit synchronization signal included in the multi-valued data signal transmitted in the form of a packet signal, a circuit for detecting by this detected output a timing of a transition of the bit synchronization signal, a circuit for sampling and holding the bit synchronization signal by using sampling pulses generated on the bases of said timing, and a circuit for decoding the multi-valued data signal by using decoding reference voltages formed on the basis of the sampled and held level.
Inventors: | Kawai; Kazuo (Yokohama, JP) |
Assignee: | General Research of Electronics, Inc. (Tokyo, JP) |
Appl. No.: | 336394 |
Filed: | November 8, 1994 |
Nov 08, 1993[JP] | 5-302320 |
Current U.S. Class: | 375/286; 375/360 |
Intern'l Class: | H04L 025/34 |
Field of Search: | 375/286,287,360,365,368,293 370/94.1,94.2,100.1,105.1,105.4,105.5,503 |
4696016 | Sep., 1987 | Rozema et al. | 375/293. |
4852124 | Jul., 1989 | Raucci | 375/293. |
5140620 | Aug., 1992 | Woodward | 375/375. |
5267267 | Nov., 1993 | Kazawa et al. | 375/294. |
5539784 | Jul., 1996 | Brauns et al. | 375/360. |