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United States Patent | 5,621,739 |
Sine ,   et al. | April 15, 1997 |
A self-testing buffer circuit. The buffer circuit utilizes an adjustable delay circuit to test whether the buffer can capture a data value during a variable stroke window. The buffer includes an input circuit coupled to receive a data value generated by the self-testing buffer circuit. The buffer circuit also includes a latch which has a latch input coupled to receive the data value from the input circuit. An adjustable delay circuit having a delay adjust input is coupled to provide an adjustably delayed strobe to a clock input of the latch. A comparison circuit may be coupled to compare a latch output value to an expected value. The self-testing buffer circuit may be used in conjunction with serial or parallel test resisters to test the buffer performance for a variety of strobe delays and data values.
Inventors: | Sine; Christopher J. (San Jose, CA); Ilkbahar; Alper (Santa Cruz, CA); Mak; Tak M. (Union City, CA) |
Assignee: | Intel Corporation (Santa Clara, CA) |
Appl. No.: | 643954 |
Filed: | May 7, 1996 |
Current U.S. Class: | 714/724; 714/733 |
Intern'l Class: | G01R 031/28 |
Field of Search: | 371/22.1,22.2,22.4,22.5,22.6,25.1,28 |
5381421 | Jan., 1995 | Dickol et al. | 371/27. |
5400057 | Mar., 1995 | Yin | 345/199. |