Back to EveryPatent.com
United States Patent | 5,619,666 |
Coon ,   et al. | April 8, 1997 |
A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
Inventors: | Coon; Brett (San Jose, CA); Miyayama; Yoshiyuki (Santa Clara, CA); Nguyen; Le Trong (Monte Sereno, CA); Wang; Johannes (Redwood City, CA) |
Assignee: | Seiko Epson Corporation (Tokyo, JP) |
Appl. No.: | 460272 |
Filed: | June 2, 1995 |
Current U.S. Class: | 712/208; 712/204; 712/215 |
Intern'l Class: | G06F 009/30; G06F 009/315 |
Field of Search: | 395/375 |
3916388 | Oct., 1975 | Shimp et al. | |
4084235 | Apr., 1978 | Hirtle. | |
4189768 | Feb., 1980 | Liptay et al. | |
4189772 | Feb., 1980 | Liptay et al. | |
4236206 | Nov., 1980 | Strecker et al. | |
4317170 | Feb., 1982 | Wada et al. | |
4454578 | Jun., 1984 | Matsumoto et al. | |
4456955 | Jun., 1984 | Yanagita et al. | |
4514803 | Apr., 1985 | Agnew et al. | |
4569016 | Feb., 1986 | Hao et al. | |
4587612 | May., 1986 | Fisk et al. | |
4654781 | Mar., 1987 | Schwartz et al. | |
4739471 | Apr., 1988 | Baum et al. | |
4771376 | Sep., 1988 | Kamiya. | |
4814976 | Mar., 1989 | Hansen et al. | |
4992931 | Feb., 1991 | Hirasawa. | |
4992934 | Feb., 1991 | Portanova et al. | |
5133072 | Jul., 1992 | Buzbee. | |
5148528 | Sep., 1992 | Fite et al. | |
5168571 | Dec., 1992 | Hoover et al. | |
5193206 | Mar., 1993 | Mills. | |
Foreign Patent Documents | |||
0170398 | Feb., 1986 | EP. | |
0272198 | Jun., 1988 | EP. | |
0380854 | Aug., 1990 | EP. | |
0461257 | Dec., 1991 | EP. | |
0473420 | Mar., 1992 | EP. | |
2230116 | Oct., 1990 | GB. |
"High Performance Dual Architecture Processor"; IBM TDB pp. 231-234; vol. 36, No. 02, Feb. 1993. Faix et al., "Combined Macro/Micro Program Machine", IBM Technical Disclosure Bulletin, vol. 14, No. 1, p. 298, Jun. 1971. Patent Abstracts of Japan, vol. 009, No. 006 (P-326), Jan. 11, 1985. S. Ohr, "Superlong Instructions Help Supermini Refine Number Crunching", Electronic Design, vol. 33, No. 26, pp. 41-43, Nov. 1985. McNeley et al., "Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer", IEEE Micro, vol. 7, No. 1, pp. 60-71, Feb. 1987. J. Wharton, "Parallel 486 Pipelines Produce Peak Processor Performance," Microprocesor Report, v3 n6 p13(5), Jun. 1989. S. Garth, "Combining RISC and CISC in PC Systems," IEEE, pp. 10/1-10/5. i486.TM. Microprocessor Programmer's Reference Manual, Order No. 240486, Intel Corporation, Santa Clara, California, 1990. i486.TM. Microprocessor Hardware Reference Manual, Order No. 240552, Intel Corporation, Santa Clara, California, 1990. J. Hennessy et al., Computer Architecture - A Quantitative Approach, Morgan Kaufman Publishers, Inc., San Mateo, California, 1990. J. Crawford, "The Execution Pipeline of the Intel i486.TM. CPU," IEEE, pp. 254-258, Feb. 26 - Mar. 2, 1990. M. Johnson, Superscalar Microprocessor Design, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1991. S. Heath, "Architecture Considerations for a M88000 Superscalar RISC Processor," IEEE, London, England, pp. 1-6, Nov. 4, 1991. Patent Abstracts of Japan, vol. 017, No. 082 (P-1489), Feb. 18, 1993. Patent Abstracts of Japan, vol. 017, No. 084 (P-1490), Feb. 19, 1993. |
______________________________________ Table of Contents ______________________________________ Detailed Description of the Preferred Embodiments 8 1.0 The Instruction Fetch Unit 8 2.0 Instruction Alignment Unit Overview 9 2.1 Instruction Alignment Unit Block Diagrams 12 3.0 Instruction Decode Unit Overview 33 3.1 Microcode Dispatch Logic 36 3.2 Mailboxes 39 3.3 Nano-Instruction Format 40 3.4 Special Instructions 41 3.5 Instruction Decode Unit Block Diagrams 43 4.0 Decoded Instruction FIFO 54 ______________________________________