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United States Patent | 5,610,874 |
Park ,   et al. | March 11, 1997 |
A synchronous random access memory device having an external address mode of operation and a burst mode of operation, in which a counter control circuit resets a burst mode counter during the external address mode of operation.
Inventors: | Park; Hee-Chail (Kyungki-do, KR); Kweon; Kook-Hwan (Kyungki-do, KR); Im; Jeon-Taek (Kyungki-do, KR) |
Assignee: | Samsung Electronics Co., Ltd. (Suwon, KR) |
Appl. No.: | 337186 |
Filed: | November 7, 1994 |
Nov 08, 1993[KR] | 23603/1993 |
Current U.S. Class: | 365/236; 365/230.01; 365/230.06; 365/233 |
Intern'l Class: | G11C 013/00; G11C 007/00 |
Field of Search: | 365/230.01,233,236,230.06 |
5077693 | Dec., 1991 | Hardee et al. | 365/230. |
5268865 | Dec., 1993 | Takasugi et al. | 365/189. |
5390149 | Feb., 1995 | Vogley et al. | 365/189. |
5392239 | Feb., 1995 | Margulis et al. | 365/233. |