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United States Patent | 5,607,773 |
Ahlburn ,   et al. | March 4, 1997 |
A method of forming a planar dielectric layer over an interconnect pattern which requires fewer processing steps and has a lower dielectric constant than is obtained in the prior art. The method comprises providing a substrate having an electrical interconnect pattern thereon, forming a first layer of dielectric over the interconnect pattern, preferably by plasma generated TEOS oxide, forming a porous second layer of silicon-containing dielectric with low dielectric constant different from the first layer over the first dielectric layer from an inorganic silicon-containing composition, preferably hydrogen silsesquioxane and forming a third layer of dielectric different from the second layer over the second dielectric layer, preferably by a plasma generated TEOS oxide. The step of forming the second layer comprises the steps of depositing an inorganic silicon-containing composition capable of being pyrolytically converted to a silicon oxide over the first layer and placing the resulting structure in an essentially pure nitrogen and essentially moisture-free environment at a pressure at or below atmospheric pressure and then heating the silicon-containing composition to a temperature of from about 375.degree. C. to about 425.degree. C. and preferably 400.degree. C. for from about 30 minutes to about 90 minutes to convert the silicon-containing composition to silicon oxide.
Inventors: | Ahlburn; Byron T. (Plano, TX); Seha; Thomas R. (Dallas, TX) |
Assignee: | Texas Instruments Incorporated (Dallas, TX) |
Appl. No.: | 359784 |
Filed: | December 20, 1994 |
Current U.S. Class: | 428/427; 257/E21.279; 257/E21.576; 427/255.6; 427/255.7; 427/294; 427/404; 427/579; 428/428; 428/448; 428/469; 428/901; 438/623; 438/624; 438/631 |
Intern'l Class: | B32B 009/00 |
Field of Search: | 427/579,294,255.7,255.6,404 428/427,428,448,469,901 |
4756977 | Jul., 1988 | Haluska et al. | 428/704. |