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United States Patent | 5,600,604 |
Chen | February 4, 1997 |
A circuit for allowing a memory module with an asymmetric addressing scheme to effectively operate with a memory controller which a symmetric address scheme is disclosed. The circuit includes a demultiplexer for receiving at least a last address bit from the memory controller and generating a plurality of control signals and a decoder. The decoder includes a plurality of decoder units. Each of the decoder units includes logic for receiving one of the plurality of control signals, a first strobe signal and a second strobe signal from the memory controller. Each of the decoder units also selectably provides a decoded second strobe signal responsive to the demultiplexer.
Inventors: | Chen; Roger (San Jose, CA) |
Assignee: | Advanced Peripherals Labs, Inc. (San Jose, CA) |
Appl. No.: | 431439 |
Filed: | May 1, 1995 |
Current U.S. Class: | 365/230.06; 365/193; 365/230.02 |
Intern'l Class: | G11C 008/00 |
Field of Search: | 365/193,230.02,230.06,189.02,233 |
4792929 | Dec., 1988 | Olson et al. | 365/193. |
5305277 | Apr., 1994 | Derwin et al. | 365/230. |
5392252 | Feb., 1995 | Rimpo et al. | 365/230. |