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United States Patent | 5,595,843 |
Dao | January 21, 1997 |
A device layer layout methodology, and method and apparatus for patterning a photosensitive layer. Device features are placed on lines running in rows and/or columns during layout. The lines and/or columns are extracted from the database to produce a layout of the phase-edge phase shifting layer. The photosensitive layer may be exposed to a mask corresponding to this layout, to produce latent image of the rows and/or lines. The photosensitive layer is also exposed to the device layer layout to expose unwanted portions of the phase-edge layer. Methods of forming a variety of device features, including contact/via openings and contact/via plugs are disclosed.
Inventors: | Dao; Giang T. (Fremont, CA) |
Assignee: | Intel Corporation (Santa Clara, CA) |
Appl. No.: | 413405 |
Filed: | March 30, 1995 |
Current U.S. Class: | 430/5; 430/311; 430/323; 430/394 |
Intern'l Class: | G03F 009/00 |
Field of Search: | 430/5,323,324,394,311 |
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