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United States Patent |
5,592,233
|
Koz
|
January 7, 1997
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Apparatus and method for video pixel data transfer
Abstract
An assembly and delivery circuit and method of operation therefor which
delivers a stream of pixel formatted digital video data as words to an
internal bus of a host personal computer. The host personal computer
receives and processes the words assembled and delivered by this circuit
to present a video image on its display screen. The assembly and delivery
circuit operates in conjunction with the host computer's internal bus at a
sufficient speed to permit a host personal computer having a sufficient
operating speed to display either black and white images, or color
television images at a real-time rate of thirty frames per second.
Inventors:
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Koz; Mark C. (731 Stanford Ave., Palo Alto, CA 94306)
|
Appl. No.:
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484298 |
Filed:
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June 7, 1995 |
Current U.S. Class: |
348/552; 348/554 |
Intern'l Class: |
H04N 009/00 |
Field of Search: |
348/571,552,554,578,844
345/150,186
|
References Cited
U.S. Patent Documents
4647968 | Mar., 1987 | Willis | 358/141.
|
4730185 | Mar., 1988 | Springer et al. | 340/701.
|
4800423 | Jan., 1989 | Appiano et al. | 358/21.
|
4811407 | Mar., 1989 | Blokker et al. | 358/903.
|
4956638 | Sep., 1990 | Larky et al. | 340/701.
|
5021873 | Jun., 1991 | Abumi | 348/160.
|
5111296 | May., 1991 | Duffield et al. | 358/903.
|
5119074 | Jun., 1992 | Greaves et al. | 340/701.
|
5138303 | Aug., 1992 | Rupel | 340/703.
|
5249164 | Sep., 1993 | Koz | 348/552.
|
5341175 | Aug., 1994 | Koz | 348/552.
|
5387945 | Feb., 1995 | Takeuchi | 348/552.
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Other References
"A Hybrid Scheme For Color Dithering," Sloan, K., Proceedings of the SPIE -
The International Society for Optical Engineering, vol. 1249, pp. 238-248.
Conference Title: Human Vision and Electronic Imaging: Models, Methods and
Applications, Conference Date: Feb. 12-14, 1990.
"Improved Dithering Methods For Colour Quantized Images," Watanabe, T.,
Transactions of the Institute of Electronics, Information and
Communication.
Engineers D-II vo. J72D-II, No. 7, pp. 985-992, Jul. 1989.
|
Primary Examiner: Peng; John K.
Assistant Examiner: Grant; Chris
Attorney, Agent or Firm: Schreiber; Donald E.
Parent Case Text
NATURE OF THIS APPLICATION
This is a division of application Ser. No. 02/292,831 filed Aug. 19, 1994,
now U.S. Pat. No. 5,502,503 which is a division of application Ser. No.
07/121,718 filed Sep. 14, 1993, which issued on Aug. 23, 1994, as U.S.
Pat. No. 5,341,175; which was itself a division of application Ser. No.
07/683,593 filed Apr. 9, 1991, which issued Sep. 28, 1993, as U.S. Pat.
No. 5,249,164. The great grandparent application Ser. No. 07/683,593 was
itself a continuation-in-part of application Ser. No. 07/545,352 filed
Jun. 27, 1990, now abandoned.
Claims
I claim:
1. A video data transfer apparatus for assembling and rapidly transferring
digital data words defining pixels of a video image to an internal bus of
a cooperating personal computer which includes a display screen upon which
the personal computer may display the video image received from said video
data transfer apparatus; the video data transfer apparatus receiving
digital data words of the video image from a video signal conversion
subsystem which converts an analog television signal into the digital data
words; said video data transfer apparatus comprising:
a video memory which receives the digital data words of the video image
from the video signal conversion subsystem and which stores the received
digital data words;
a video data transfer controller which transmits a signal that informs the
personal computer when digital data words of the video image are present
in said video memory, and which subsequently receives from the personal
computer a command to transfer, to the internal bus of the personal
computer, digital data words of the video image; and
word buffers that operate in response to load signals received from the
video data transfer controller for respectively receiving from said video
memory and temporarily storing digital data words of the video image, and
then the word buffers, in response to a transfer signal received from the
video data transfer controller, transfer, to the internal bus of the
personal computer, the digital data words of the video image, which is
present in the word buffers, whereby the personal computer may display the
video image of the analog television signal on the display screen in
real-time.
2. The video data transfer apparatus of claim 1 wherein said word buffers
in said video data transfer apparatus comprise four eight-bit buffers
adapted to transfer thirty-two data bits for use in the cooperating
personal computer which uses data words of thirty-two bits.
3. The video data transfer apparatus of claim 2 wherein all but one of said
word buffers are latched uni-directional buffers, and the remaining one of
said word buffers is a bi-directional buffer adapted to receive control
signals from the cooperating personal computer.
4. The video data transfer apparatus of claim 1 wherein said video data
transfer controller includes:
a programmable gate array logic integrated circuit for transmitting the
signal that informs the personal computer when digital data words are
present in said video memory, for receiving the command from the personal
computer to transfer to the internal bus of the personal computer digital
data words of the video image, and for producing both the load signals and
the transfer signal to which said word buffers respond; and
a read only memory for storing software instructions loaded into said
programmable gate array logic integrated circuit.
5. The video data transfer apparatus of claim 4 wherein said read only
memory also stores a driver program that is loaded into and executed by
the cooperating personal computer to effect picture control and decoding
operations of the personal computer.
6. The video data transfer apparatus of claim 1 wherein said video data
transfer controller includes a read only memory for storing a driver
program that is loaded into and executed by the cooperating personal
computer to effect picture control and decoding operations of the personal
computer.
7. The video data transfer apparatus of claim 1 wherein all but one of said
word buffers are latched uni-directional buffers, and the remaining one of
said word buffers is a bi-directional buffer adapted to receive control
signals from the cooperating personal computer.
8. The video data transfer apparatus of claim 1 wherein each digital data
word defines a pixel of a black and white video image.
9. The video data transfer apparatus of claim 1 wherein each digital data
word defines a pixel of a color video image.
10. In an apparatus for displaying on a display screen of a personal
computer a video image specified by digital data words defining pixels of
the video image, the apparatus including a video data transfer apparatus
which receives digital data words of the video image from a video signal
conversion subsystem that converts an analog television signal into the
digital data words, said video data transfer apparatus also assembling and
rapidly transferring digital data words directly to an internal bus of the
personal computer, the improvement comprising:
a video memory which receives the digital data words of the video image
from the video signal conversion subsystem and which stores the received
digital data words;
a video data transfer controller which transmits a signal that informs the
personal computer when digital data words of the video image are present
in said video memory, and which subsequently receives from the personal
computer a command to transfer, to the internal bus of the personal
computer, digital data words of the video image; and
word buffers that operate in response to load signals received from the
video data transfer controller for respectively receiving from said video
memory and temporarily storing digital data words of the video image, and
then the word buffers, in response to a transfer signal received from the
video data transfer controller, transfer, to the internal bus of the
personal computer, the digital data words of the video image, which is
present in the word buffers, whereby the personal computer may display the
video image of the analog television signal on the display screen in
real-time.
11. The video data transfer apparatus of claim 10 wherein said video data
transfer controller includes:
a programmable gate array logic integrated circuit for transmitting the
signal that informs the personal computer when digital data words are
present in said video memory, for receiving the command from the personal
computer to transfer to the internal bus of the personal computer digital
data words of the video image, and for producing both the load signals and
the transfer signal to which said word buffers respond; and
a read only memory for storing software instructions loaded into said
programmable gate array logic integrated circuit.
12. The video data transfer apparatus of claim 11 wherein said read only
memory also stores a driver program that is loaded into and executed by
the cooperating personal computer to effect picture control and decoding
operations of the personal computer.
13. The video data transfer apparatus of claim 10 wherein said video data
transfer controller includes a read only memory for storing a driver
program that is loaded into and executed by the cooperating personal
computer to effect picture control and decoding operations of the personal
computer.
14. The video data transfer apparatus of claim 10 wherein said word buffers
in said video data transfer apparatus comprise four eight-bit buffers
adapted to transfer thirty-two data bits for use in the cooperating
personal computer which uses data words of thirty-two bits.
15. The video data transfer apparatus of claim 14 wherein all but one of
said word buffers are latched uni-directional buffers, and the remaining
one of said word buffers is a bi-directional buffer adapted to receive
control signals from the cooperating personal computer.
16. The video data transfer apparatus of claim 10 wherein all but one of
said word buffers are latched uni-directional buffers, and the remaining
one of said word buffers is a bi-directional buffer adapted to receive
control signals from the cooperating personal computer.
17. The video data transfer apparatus of claim 10 wherein each digital data
word defines a pixel of a black and white video image.
18. The video data transfer apparatus of claim 10 wherein each digital data
word defines a pixel of a color video image.
19. A method for receiving digital data words defining pixels of a video
image from a video signal conversion subsystem which converts an analog
television signal into the digital data words; and for assembling and
rapidly transferring the digital data words directly to an internal bus of
a cooperating personal computer which includes a display screen upon which
the personal computer may display the received video image; said method
comprising the steps of:
receiving digital data words of the video image from the video signal
conversion subsystem and storing the received digital data words into a
video memory;
after digital data words are present in the video memory, transmitting a
signal to the personal computer which informs the personal computer that
the digital data words are present; and
repetitively receiving commands from the personal computer to transfer, to
the internal bus of the personal computer, digital data words of the video
image, and in response to each command received from the personal
computer:
transferring digital data words of the video image from the video memory
into word buffers until the word buffers have received, and are
respectively temporarily storing, at least one digital data word of the
video image; and
transferring at least one digital data word of the video image, which is
present in the word buffers, from the word buffers to the internal bus of
the personal computer;
until the digital data words of the video image have been transferred from
the video memory to the internal bus of the personal computer, whereby the
personal computer may display the video image of the analog television
signal on the display screen in real-time.
20. The method of claim 19 wherein the internal bus of the cooperating
personal computer uses data words having thirty-two bits.
21. The method of claim 20 wherein each digital data word defining a pixel
of the video image contains eight bits.
22. The method of claim 20 wherein each digital data word defining a pixel
of the video image contains twenty-four bits.
23. The method of claim 19 wherein each digital data word defines a pixel
of a black and white video image.
24. The method of claim 19 wherein each digital data word defines a pixel
of a color video image.
25. A video data transfer apparatus for assembling and rapidly transferring
digital data words defining pixels of a video image to a bus of a
cooperating computer which includes a display screen upon which the
computer may display the video image received from said video data
transfer apparatus; said video data transfer apparatus comprising:
a video memory which receives the digital data words of the video image and
which stores the received digital data words;
a video data transfer controller which transmits a signal that informs the
computer when digital data words of the video image are present in said
video memory, and which subsequently receives from the computer a command
to transfer, to the bus of the computer, digital data words of the video
image; and
word buffers that operate in response to load signals received from the
video data transfer controller for respectively receiving from said video
memory and temporarily storing digital data words of the video image, and
then the word buffers, in response to a transfer signal received from the
video data transfer controller, transfer, to the bus of the computer, the
digital data words of the video image, which is present in the word
buffers.
26. The video data transfer apparatus of claim 25 wherein said video data
transfer controller includes:
a programmable gate array logic integrated circuit for transmitting the
signal that informs the computer when digital data words are present in
said video memory, for receiving the command from the computer to transfer
to the bus of the computer digital data words of the video image, and for
producing both the load signals and the transfer signal to which said word
buffers respond; and
a read only memory for storing software instructions loaded into said
programmable gate array logic integrated circuit.
27. The video data transfer apparatus of claim 26 wherein said read only
memory also stores a driver program that is loaded into and executed by
the cooperating computer to effect picture control and decoding operations
of the computer.
28. The video data transfer apparatus of claim 26 wherein said video data
transfer controller includes a read only memory for storing a driver
program that is loaded into and executed by the cooperating computer to
effect picture control and decoding operations of the computer.
29. The video data transfer apparatus of claim 26 wherein said word buffers
in said video data transfer apparatus comprise four eight-bit buffers
adapted to transfer thirty-two data bits for use in the cooperating
computer which uses data words of thirty-two bits.
30. The video data transfer apparatus of claim 29 wherein all but one of
said word buffers are latched uni-directional buffers, and the remaining
one of said word buffers is a bi-directional buffer adapted to receive
control signals from the cooperating computer.
31. The video data transfer apparatus of claim 26 wherein all but one of
said word buffers are latched uni-directional buffers, and the remaining
one of said word buffers is a bi-directional buffer adapted to receive
control signals from the cooperating computer.
32. The video data transfer apparatus of claim 26 wherein each digital data
word defines a pixel of a black and white video image.
33. The video data transfer apparatus of claim 26 wherein each digital data
word defines a pixel of a color video image.
34. In an apparatus for displaying on a display screen of a computer a
video image specified by digital data words defining pixels of the video
image, the apparatus including a video data transfer apparatus which
receives digital data words of the video image for assembling and rapidly
transferring digital data words directly to a bus of the computer, the
improvement comprising:
a video memory which receives the digital data words of the video image and
which stores the received digital data words;
a video data transfer controller which transmits a signal that informs the
computer when digital data words of the video image are present in said
video memory, and which subsequently receives from the computer a command
to transfer, to the bus of the computer, digital data words of the video
image; and
word buffers that operate in response to load signals received from the
video data transfer controller for respectively receiving from said video
memory and temporarily storing digital data words of the video image, and
then the word buffers, in response to a transfer signal received from the
video data transfer controller, transfer, to the bus of the computer, the
digital data words of the video image, which is present in the word
buffers.
35. The video data transfer apparatus of claim 34 wherein said video data
transfer controller includes:
a programmable gate array logic integrated circuit for transmitting the
signal that informs the computer when digital data words are present in
said video memory, for receiving the command from the computer to transfer
to the bus of the computer digital data words of the video image, and for
producing both the load signals and the transfer signal to which said word
buffers respond; and
a read only memory for storing software instructions loaded into said
programmable gate array logic integrated circuit.
36. The video data transfer apparatus of claim 35 wherein said read only
memory also stores a driver program that is loaded into and executed by
the cooperating computer to effect picture control and decoding operations
of the computer.
37. The video data transfer apparatus of claim 34 wherein said video data
transfer controller includes a read only memory for storing a driver
program that is loaded into and executed by the cooperating computer to
effect picture control and decoding operations of the computer.
38. The video data transfer apparatus of claim 34 wherein said word buffers
in said video data transfer apparatus comprise four eight-bit buffers
adapted to transfer thirty-two data bits for use in the cooperating
computer which uses data words of thirty-two bits.
39. The video data transfer apparatus of claim 38 wherein all but one of
said word buffers are latched uni-directional buffers, and the remaining
one of said word buffers is a bi-directional buffer adapted to receive
control signals from the cooperating computer.
40. The video data transfer apparatus of claim 34 wherein all but one of
said word buffers are latched uni-directional buffers, and the remaining
one of said word buffers is a bi-directional buffer adapted to receive
control signals from the cooperating computer.
41. The video data transfer apparatus of claim 34 wherein each digital data
word defines a pixel of a black and white video image.
42. The video data transfer apparatus of claim 34 wherein each digital data
word defines a pixel of a color video image.
43. A method for receiving digital data words defining pixels of a video
image; and for assembling and rapidly transferring the digital data words
directly to a bus of a cooperating computer which includes a display
screen upon which the computer may display the received video image; said
method comprising the steps of:
receiving digital data words of the video image and storing the received
digital data words into a video memory;
after digital data words are present in the video memory, transmitting a
signal to the computer which informs the computer that the digital data
words are present; and
repetitively receiving commands from the computer to transfer, to the bus
of the computer, digital data words of the video image, and in response to
commands received from the computer:
transferring digital data words of the video image from the video memory
into word buffers until the word buffers have received, and are
respectively temporarily storing, at least one digital data word of the
video image; and
transferring at least one digital data word of the video image, which is
present in the word buffers, from the word buffers to the bus of the
computer;
until the digital data words of the video image have been transferred from
the video memory to the bus of the computer.
44. The method of claim 43 wherein the bus of the cooperating computer uses
data words having thirty-two bits.
45. The method of claim 44 wherein each digital data word defining a pixel
of the video image contains eight bits.
46. The method of claim 44 wherein each digital data word defining a pixel
of the video image contains twenty-four bits.
47. The method of claim 43 wherein each digital data word defines a pixel
of a black and white video image.
48. The method of claim 43 wherein each digital data word defines a pixel
of a color video image.
Description
TECHNICAL FIELD
The invention is in the field of video display on a personal computer (PC).
More particularly, it concerns the display of a television (TV) picture or
other analog visual signal on a portion of the cathode ray tube (CRT) or
monitor of a PC while the PC is running other programs. The invention
comprises a standard plug-in card for a desk-type computer or work
station, on which card is an all-channel television tuner which is adapted
to continuously tune through all standard television channels as well as
the broadcast FM frequency spectrum, and all necessary circuitry and
components to demodulate the selected TV signal (or other similar analog
visual signal, such as a closed-circuit surveillance, test monitoring or
security system camera or playback from a video cassette recorder (VCR),
digitize it, store these digitally encoded signals in a temporary memory,
and through a novel multi-word buffer stage transfer the stored signals to
the computer when requested during its operating cycle for display in a
selected portion of its screen along with other displayed material under
control of the host computer's central processor. The invention will
produce picture data for display at a rate of thirty picture frames per
second, which is the standard transmitted rate of broadcast and/or
closed-circuit television. This picture frame rate is required for smooth
motion display, and will be referred to in this specification as "real
time" display or processing. In its color version, the invention also
provides a slower picture display of much higher resolution, in a freeze
frame or similar mode.
The invention described primarily herein will be referred to as the
DigiVideo, particularly meaning its color version. Two different sizes of
picture display on the associated PC may be produced. The invention is
most efficiently adaptable to a computer which uses 32-bit words and has
sufficient operating speed to achieve real time display, thus being
particularly compatible with the Macintosh II. It is this version which
will be described in detail, although the invention could be adapted to be
functional in the large group of computers known as IBM (International
Business Machines) compatibles and/or clones, using a common basic
processing scheme and language, Micro-soft Disk Operating System (DOS)
having resident either Windows 386 or Operating system/2 (OS/2). While the
invention could be adaptable to the UNIX software system, in its present
form it would be unable to accommodate display of 30 picture frames per
second. Certain processing differences are required by variations in basic
personal computers.
(The disclosure will include an earlier black and white design operating in
the same manner. The black and white version provided two models
delivering different picture sizes, called the MicroTV for the smaller
display, DigiVideo for a unit capable of producing both display sizes.)
BACKGROUND ART
The basic processing scheme of a personal computer does not directly
facilitate display of visual images showing continuous motion, as
particularly exemplified by standard television transmissions. Processing
and displaying pictures at this real time rate involves handling a
relatively large data stream.
It can readily be seen there are numerous potential uses for the capability
of viewing a motion picture or TV type image on an inset portion of a PC
screen. In addition to merely watching television, surveillance and
security systems come to mind--comparing a closed-circuit view of a person
with file copies of photographs and clearance or authorization, for
example. Viewing of testing operations (e.g.: wind tunnels or displays of
changing data such as oscillographs monitored by remote cameras) while
reviewing or correcting calculated data is another possibility. Reviewing
forensic simulations on magnetic tape recordings while preparing or
reviewing commentary or testimony is another, as well as comparison of
still file photographs therewith. Other applications are not difficult to
conceive.
Visual images for display on a PC are made up of pixels, or discrete image
elements, each pixel requiring an eight bit word for definition. It can be
seen that the operating speed of a PC will determine whether or not it is
possible to achieve motion display with the smoothness which is
characteristic of the standard thirty frame per second real time rate.
When the PC lacks sufficient speed to display real time motion, edited or
intermittent motion display could still be very useful in many
applications.
Prior art methods transmit only one pixel of video at a time on the
computer's internal bus, resulting in a transmission time of as much as
one second or more for a black and white image, considerably longer for
color, which is clearly inadequate for smooth display of images involving
motion.
Prior art devices for achieving display of moving images on a PC screen
from analog sources have customarily provided extra processing capability
to bypass the internal computer bus cycle processing or reduce the machine
time required for the picture display. This results in an increase in
equipment expense, as processors are relatively expensive, as well as
increasing the bulk and installation complexity of the equipment.
Applicant is aware of two current art products which seek to achieve a
result similar to the current invention.
1. A device called the MassMicro, selling for about $3,000, it is believed.
This device requires two plug-in cards and includes its own video output
card, producing a video overlay which it mixes directly with the picture
displayed by the PC. The host PC's main processor never sees the data
being processed by the MassMicro.
2. A device called the OrangeMicro, selling for about $4,000, it is
believed. This device also requires two plug-in cards, and has its own
processor, taking over the PC data bus as a bus master processor, so again
the PC main processor never sees the data being handled by this device.
In addition to their expense, their requirement for two expansion slots in
the PC, and their interference with control by the host PC, neither of
these devices is capable of the data delivery speed necessary for smooth
motion display on the PC screen.
The current invention provides, on a single plug-in video card at a much
lower cost than either of the above-mentioned devices, smooth video motion
at up to thirty frames per second. The current invention not only
provides, by its novel data transfer stage, picture data at a much higher
rate than either of the above devices, but does so under the master
control of the host PC, rather than overriding its processing, as do the
two devices mentioned above.
DISCLOSURE OF THE INVENTION
The invention comprises a plug-in computer card on which are disposed an
all-channel television (TV) tuner and accompanying circuitry to provide a
continuous TV picture which the user can display on a chosen portion of a
computer screen. The display is controlled by the computer operator with
software provided with the invention in conjunction with the basic
operating system for the PC, while the PC is simultaneously used for other
processing tasks.
The invention has the capability of providing to a PC for display on its
screen an inset or overlay picture. While the mode of processing is
essentially unchanged, the invention is available in models providing
different capabilities: the frame displayed may be 128.times.128 pixels in
the earlier black and white MicroTV model, the later models (DigiVideo,
both color and black and white) provide either 128.times.128 pixels or
256.times.256 pixels, depending upon the machine and software with which
it is used. Clearly, the larger picture requires four times as many pixels
as the smaller, transmitted in the same period of time if real time
display is to be achieved, which puts a premium on machine speed and
capacity. In those personal computers having sufficient operation speed
(e.g. the Macintosh II) this invention makes possible this real time
display by transmitting pixels of picture data at a much higher rate than
prior art methods.
For use for TV reception, an external antenna is required, and a standard
F-type connector is provided. An additional F-type plug is provided for an
alternate analog source, such as a video cassette recorder, and RCA
pin-plug connectors are provided for separate audio input and output.
This disclosure section will discuss the color model and will reference the
numbers on the system block diagram FIG. 1; subsequently the simpler black
and white processing will be addressed. For simplicity the description
herein will be addressed to TV reception displayed on a Macintosh II
personal computer, but one skilled in the art can see how other sources
may be substituted, and illustrative changes required for IBM compatible
applications will be stated. It is noted, however, that all internal
clocking for the DigiVideo processing is derived from the Macintosh 10 MHz
clock, so that to use another computer clock changes may be required. It
is further noted that in FIG. 1, control lines for the Intelligent
Instruments Communications (I2C herein, a registered trademark of Phillips
Signetics, a two line system using a clock line and a signal pulse line)
system are not shown; instead each element controlled thereby is noted on
the diagram in the bottom right corner of the element block.
In summary, the DigiVideo standard plug-in card for the Macintosh II
connects with the Macintosh internal processing bus designated as the
NuBus. The sequence of processing within the invention and within the host
Macintosh computer is controlled by system software resident in a
read-only memory (ROM) in the NuBus Driver and Xilinx configuration
component 51. When the system is powered, this program loads instructions
into the Xilinx field programmable gate array 50, and also loads a NuBus
driver program into the Macintosh, for its picture control and decoding
operations.
1. The desired channel of TV reception (or FM frequency) may be selected by
keyboard control, or with the mouse, using software provided with the
invention and installed in the PC. The software provides for tuning the TV
tuner by voltage controlled oscillator (VCO), utilizing "look-up" tables
for the control frequency for each channel and for the voltage to the VCO
to tune that frequency. Frequency control and stability are provided by
the phase-locked-loop design of the tuner utilized. The actual tuning, as
well as other switching and control operations within the invention, is
controlled by use of the I2C control system mentioned above.
The incoming signal from the TV tuner goes to a tuner/IF (intermediate
frequency) Processor (21) which comprises two sections. The front end
comprises a Phase Locked Loop (PLL) television band tuner which also
includes the FM (frequency modulated) radio broadcast band. The tuner
utilized in the invention is capable of continuous tuning from 50 to 809
Megahertz (MHz) of television broadcast channels, including frequency
modulated (FM) broadcasts only in the FM radio broadcast band.
In the tuner section of this processor, the received RF is converted to a
45 MegaHertz (MHz) IF signal, which in the second section of the processor
is detected to obtain an NTSC (National Television Standards Committee)
video signal.
The output of the initial processor is directed to a video-audio
multiplexer (22), which is essentially an analog switch to provide
selection of either video from the tuner-processor or one of the alternate
input from the other connector. This selection is again controlled by the
I2C serial control system under computer control.
2. The audio signal from the video/audio multiplexer (hereinafter mux) is
directed to an audio amplifier (23) and an audio switch (24) which
switches it to either an external audio output pin-plug or to an internal
speaker on the DigiVideo board. The DigiVideo in its current form does not
provide for demodulation and reproduction of standard FM radio broadcasts,
but available components could provide this capability.
3. The video is directed both to an NTSC to RGB (red-green-blue) converter
or video signal conditioning unit (31) and to a video synchronization
(hereinafter sync) signal stripper (33).
The received television signal is processed in the video signal conditioner
(31) which demodulates the video signal, and separates it into its color
components indicating red, green and blue, the demodulation frequency is
crystal stabilized at 3.579545 MegaHertz (MHz). Transfer of color
components is controlled by the 10 MHz NuBus clock in the host Macintosh
computer, which clock signal controls all DigiVideo functions. In the
signal conditioner, and in data transfer, the clock signal is divided
according to the frame size selected--If the picture is 256.times.256
pixels, the storage and delivery clock rate is 5MHz; if it is
128.times.128 pixels, the clock rate is 2.5MHz.
Each of these color components is sent to one of three identical seven-bit
analog to digital (A-D) converters (42, 43, and 44). These signals are
also directed to an analog multiplexer 41 which selects either an 8-bit
color mode for real time display or a 24-bit color mode for high
resolution display.
The video signal conditioner is adapted to demodulate and process either
the 3.5MHz frequency band for United States standard TV broadcasts, or the
4.4MHz band for the PAL (Phase Alternate Line) system used in European
broadcasts, in which the latter case the crystal reference frequency is
4.43 MHz.
The converter is controlled by a picture attribute controller (32) (again
as directed by the host computer through the I2C control lines). This
controller is an octal digital-analog controller using direct current (DC)
drive level control to control several functions: hue, saturation,
contrast and brightness in the television picture, as well as audio
volume. The attribute controller also controls the level of a drive signal
to (35), a novel picture enhancement circuit.
The video sync stripper (33) extracts the vertical and horizontal
synchronization pulses from the video signal and provides them on separate
lines to a Xilinx (TM) field programmable gate array with controls the
delivery of the output data words to the Macintosh NuBus, as described
hereinafter.
The video signal conditioning process includes a picture enhancement
circuit 35, also referred to herein as a dither control. The reference
voltage and ground from the color component A-D converters (42, 43, and
44) are reintroduced into the NTSC to RGB converter or signal conditioner
31 after digitization in a positive feedback mode (FIG. 2 at 35b). These
references carry a noise signal from the digitization which enhances the
noise of the color component signals in a random manner. The feedback
enhancement is limited by a "dither control" (FIG. 2 at 35a), so the
increased noise signal is controlled to that level which will, when
converted in the three separate color-band A-D converters, affect the
least significant bit of the three (or two) bit signals for the color
bands. This least significant bit will then dither, or change state
somewhat randomly, so that a color transition in the lower intensity edge
of each separate color-band signal will then change in a more or less
gradual (and unpredictable) manner rather than by a step change as is
characteristic of digital decoding. This sloped rate of change of the
lower intensity border or each of the primary colors will produce a
varying and somewhat random range of shades within the spectrum defined in
the received video signal. Since this dithering of the least significant
bit in each of the three color-band signals is gaussian in its
distribution, the interaction of the independent signals will cross over
the discrete color spot boundaries on the computer video card and produce
many more than the standard 256 colors produced by a clean or
noise-filtered video signal. Since the eye perceives the
thirty-frame-per-second screen display as smooth motion, it will also
blend the random variance of the color-edges between the red-green-blue
pixels as many more slight variations or shades in color, in a number
which cannot be accurately determined.
4. In converter (31), the video picture signal is separated into red, green
and blue components. Each of these components is directed to a 7-digit
digital-to-analog (A-D) converter (42, 43, and 44) which continuously
convert the analog video color component streams into seven-bit digital
words, each separate stream defining a color component for display on the
PC screen.
The red, green and blue color components (analog) are directed to analog
multiplexer (mux, also called a 24-bit frame grab control) 41 which, as
directed by system software (gate array transfer control 50 through the
I2C link) selects between two color word modes for storage and display
(see FIG. 1):
a: In what may be termed the real time (eight-bit color) mode, analog mux
41 directs A-D converter 42 to the eight-bit color mode. In this mode, the
green component signal is transferred by analog mux 41 to A-D converter
42, while the red signal goes direct to A-D converter 43 and the blue
signal to A-D converter 44. Data buffer 46 continuously accepts eight-bit
color words (three red, three green, two blue) and transfers them for
storage in video frame memory 47, from which complete video frames are
transferred to the host computer NuBus, as described subsequently.
Timing of processing the A-D conversion and storage is based on the
vertical sync pulse which begins each TV frame; eight-bit words are read
out 256 for each line (in the larger size display) for 256 lines, clocked
by the horizontal sync pulse (63.5 microsecond intervals). After a
complete frame is stored in video frame memory 47, the computer is
signalled and the DigiVideo waits for a command to transfer the picture
frame.
b. In an alternative mode providing a slow rate non-real-time display of
much higher resolution (and many more color shades), analog mux 41 and
data buffer 45 are commanded to assemble 24-bit color words, each of all
one color (21 color bits from three seven-bit words, plus three dummy
bits). Mux 41 selects the proper color component and transfers it to A-D
converter 42, which provides seven-bit color words to data buffer 45 for
storage in memory 47. In this mode, an entire frame of red signals is
assembled and transferred to the computer, then a frame of green, then of
blue. Software provided with the invention for the Macintosh provides for
display of a resultant high-resolution color frame at a slow repetition
rate, in what might be considered a freeze frame mode. It might be noted
that the dither circuit has very little effect in this color mode.
5. Data transfer to the PC is controlled by the Xilinx programmable gate
array, according to instructions loaded at power on as initially
described.
a. When a complete TV picture has been assembled in the memory, the
DigiVideo transmits a signal to the PC processor that a picture frame is
ready.
b. When the main PC program is ready to read the picture for display, it
addresses the DigiVideo by a signal known in Macintosh language as
"myslot", initiating data readout from that source in time intervals of
500 nanoseconds .vertline.ns.vertline. each.
c. During the allotted 500ns interval, the MicroTv Receives a clock signal
every 100ns from the Macintosh PC: On the "myslot" pulse, the controller
in the invention's novel data transfer stage directs transfer of video
data from the RAM to four output registers or buffers, the first three of
which are uni-directional latched buffers, the fourth being
bi-directional. On each of the four successive clock counts at 100 ns
intervals, an eight-bit data word describing a pixel of information is
transferred in parallel into one of the four eight-bit output registers,
in order. On the fourth clock pulse in addition to loading the data word
in the fourth buffer, the controller directs output in parallel of all
four words to the PC which accepts them in correct order as one 32-bit
word for Macintosh processing. The DigiVideo then acknowledges and signals
ready again.
d. The PC continues to address the DigiVideo under its program control,
each sample time being 500 ns, during which time four pixels are
transferred as described in 7 above, the sample rate being determined by
program rate and relative priority, as described below. When the complete
picture has been read, the MicroTv assembles another complete frame in its
RAM, signals the PC that a complete picture is ready and the process
repeats under control of the PC program.
To read out data for a 128.times.128 pixel array, the above-described 500ns
readout cycle must occur 4096 times per complete picture frame, or 122,880
times per second, which amounts to slightly over six one-hundredths of a
second (or 6% of machine time) consumed in this data transfer process. For
a display array of 256.times.256 pixels, these numbers are correspondingly
16384 times per picture frame, or 491,520 times per second, approximately
24% of machine time. Internal PC processing time is additional, and
display of the picture may consume a significant part of the PC operating
cycle, particularly for the 256.times.256 pixel picture.
The data output transfer sequence (DOT for short) is precisely the same in
the color and in the earlier black and white models. In the earlier
models, readout and storage control is exercised by a PAL (programmable
array logic) which has the control sequence permanently "burned" in. See
below for code. In the color model, as described above, a Read Only Memory
(51) supplies the program both to the gate array circuit 50 for internal
control and to the computer as a NuBus driver. Communication with the
Macintosh are through a bi-directional buffer 55--see FIGS. 3 and 5.
Original IBM machines used either an eight-bit or sixteen-bit word, however
computers appear almost daily with increased speed and capacity.
For example, the original IBM PC, using eight-bit words at 4.77 megahertz
(MHz) operating speed, could only read one word at a time, so the
multi-word output buffer circuit would not help. That particular machine
could not display a real time picture. Internal PC processing, not
included in this invention, could provide a slower than real time picture
display. Later models of IBM machines operate at high speeds and have
progressed to longer operating words, which could provide real time
display.
Other computers recently appearing on the market feature greatly higher
operating speeds and some besides the Macintosh now use thirty two bit
words, so the preferred mode of the invention described herein could be
directly adaptable to them, depending on internal logic, clock frequency
and processing mode.
Again, internal machine processing time for display must be considered to
determine utility of the process.
A logic difference between the two types of machines requires attention. A
Macintosh reads zero as "white" on its video card, while IBM reads a
digital one as white. So the A-D converter in different versions of the
DigiVideo must accommodate this logic inversion.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1, 1a and 1b are block diagrams of the invention in its color
DigiVideo version, adapted as a data flow diagram, showing all components
of the invention mounted on the plug-in card, with the exception of the
card connector to the PC, which is shown in FIGS. 3 and 5.
FIGS. 2, 2a and 2b are circuit diagrams of a portion of the video
demodulation and conditioning circuitry with that portion constituting the
dither circuit indicated.
FIG. 3 is a block diagram of the novel data output circuit of the invention
in its color version form, providing the capability to transfer the
picture to the host PC in real time if the PC is capable of that speed.
FIG. 4 is a block diagram of the black and white version of the invention,
analogous to FIG. 1.
FIG. 5 is the black and white version of the data output circuit.
FIG. 6 is the software flow diagram for operation of the DigiVideo and its
readout by the Macintosh PC.
In FIGS. 1, 3 and 5 double lines indicate digital data transfer in
parallel; data transfer is indicated on FIG. 4.
DESCRIPTION OF THE PREFERRED EMBODIMENT
This detailed description will apply to the color version of the invention
specifically adapted to the Macintosh II or subsequent models in that
series. Adaptability of the invention to the IBM type machines has been
indicated hereinbefore, but will not be discussed in detail.
The operation of the DigiVideo is controlled by software provided with the
machine. The flow diagram of operations is shown in FIG. 6, and the entire
software program, which is in Read Only Memory (ROM) in NuBus driver and
Xilinx configuration controller 51 is attached hereto as Appendix 1.
Referring first to FIG. 1, at the right of the figure the number 10
represents signal sources for the invention described herein, as well as
an audio output monitor. At 11 is indicated connection of an antenna for
reception of a standard TV broadcast signal, at 12 an alternate signal
source, such as a video-cassette recorder, closed-circuit TV, or other
analog source whose signal characteristics are compatible with analog TV
signal processing. Also indicated are provisions for an external audio
source 13 and an external audio monitor 14 which may be used by the
invention. By external switching, not a part of the invention, more than
one alternate source may be used.
Signal sources 11 and 12, are connected to the invention through F-type
connectors, 13 and 14 by RCA pin-type connectors. These connectors are on
the frame edge of the computer card 20 on which the invention is disposed.
This is a standard card for the Macintosh II or subsequent models of that
series of computers. The card dimensions are 4.times.13 inches
(10.16.times.323.02 mm), with a 96-pin connector, indicated at 28, mating
with the PC.
On the plug-in card 20 are disposed the elements of the color DigiVideo,
which will be specified by part numbers. Additional discrete circuitry for
voltage control is according to standard practice known to one skilled in
the art.
A. A first processing stage, comprising
an all-channel standard TV tuner combined with an intermediate frequency
(I/F) processor 21, UV936, Phillips;
a switching control unit or video/audio multiplexer (mux) 22, TDA8440N;
an audio chain consisting of an amplifier 23, LM324AD, an audio switch 24
and a miniature loudspeaker 25, both of standard design, and an audio
output plug;
B. A video processing stage:
video signal conditioner (NTSC to RGB converter) 31, TDA3567N;
picture attribute control 32, TDA8444N, which also provides audio volume
control and a novel "dither" circuit (35) see FIG. 2 and discussion;
a differential voltage control 34, LM78L05, which supplies reference
voltage (2 volts) for the analog to digital conversion;
C. Analog to digital conversion and storage stage;
a 24-bit "frame grab control" 41, 74HC4051, which selects, on command,
either an 8-bit real time color mode or a slower 24-bit high resolution
color frame display;
three identical seven-bit digital-to-analog (D-A) converters, 42, 43 and
44, (MC10321), one each for red, green and blue color signals;
a data buffer 45, 74LS540 which transfers the color data frame to the RAM
storage memory if the 24-bit color mode is selected;
a data buffer 46, also 74LS540, which transfers the color data to the RAM
storage in the eight-bit mode, which is standard PC video color of three
red bits, three green bits and two blue bits;
a video frame memory (RAM storage) 47, 43256-100, which stores a full video
frame for readout to the PC;
D. The data transfer (data output transfer, or DOT) stage which delivers
color data words to the computer;
a Xilinx field programmable gate array 50, XC2018PC84-70, which follows
instructions loaded therein on power-up, and controls the operations of
the DigiVideo, including data delivery (also referred to as a controller);
a NuBus driver & Xilinx configuration ROM 51, NS27C64-200. This circuit
holds the instructions for gate array 50 as well as the software program
for the Macintosh PC. On initial power-up of the DigiVideo, gate array 50
is configured and, on request from the PC, the NuBus driver containing all
DigiVideo interface instructions is loaded therein through bi-directional
buffer 55.
uni-directional data buffers 52, 53, and 54 (each 74F534) and
bi-directional buffer 55 (74ALS640), which deliver four eight-bit words to
the PC at one time as a 32-bit data word. These buffers are identical in
the color and black and white versions of the invention.
Referring to FIG. 2, a portion of the circuitry including NTSC to RGB
processor 31 is shown. The novel dither control of the invention, the
operation of which has been described in general above, is indicated
herein at 35a and 35b.
The ground and reference voltage from the three color component A-D
converters 42, 43 and 44, which after signal processing in those
converters are now carrying a noise signal, are reintroduced into signal
conditioner 31 as indicated at 35b. This noise signal, in a positive
feedback mode, will cause the three color components to vary, or "dither"
somewhat randomly, since the noise is gaussian in distribution. The dither
control voltage signal, introduced through the network shown at 35a, to
the filter and peak elements of the signal conditioner, limits the amount
of variation allowed in the signal to that level which will, as previously
summarized, cause the least significant bit to vary randomly. This dither
is effective in the eight-bit color mode, but much less so in the 24-bit
high resolution mode.
Referring to FIG. 3, the elements of the invention's novel data transfer
and control stage are shown to explain the operation of the device. Also
shown, designated 28, is the 92-pin connector which mates the card to the
Nubus in the Macintosh II PC. In FIG. 3, double lines represent data
transfer in parallel over eight lines for the eight-bit words used to
define picture pixels. The ultimate bit numbers for the final 32-bit word
transferred to the Macintosh II are indicated by the corresponding pin
numbers on connector 28 to which they are addressed, in four-bit groups
(AD0, AD4, etc, through AD28). Control signal flow is shown in lighter
lines.
Other than the four signals marked at the top of the figure, data transfer
between the Macintosh and the DigiVideo are through bi-directional buffer
55.
The elements of this novel input-output control and data transfer device
are stated above.
Communication of the invention with the PC is through connector 28. The
following signals are required for control and data transfer:
a signal called NMRQ (non-maskable interrupt data request), is sent by
controller 50 to the PC via pin 31 of connector 28, to inform the PC that
a complete picture frame is ready in the RAM for transfer;
the signal called "myslot" in Macintosh language, is received by the
invention (controller 50) on pin 92;
the clock signal (every 100ns) is received on pin 96 to go to the
controller 50, and provided by the controller to the other elements of the
DigiVideo which are clock synchronized;
the "ready" or "acknowledge" is returned on pin 28;
address code and I2C control signals are received on the eight pins
designated which communicate with bi-directional buffer 55 (pin-pairs 82 &
18, 83 & 19, 84 & 20 and 85 & 21). The eight-pin data bus as designated on
FIG. 2 goes to the memory 47 and the IIC controller 27 shown in FIG. 1,
previously described.
On "myslot", controller 50 directs transfer of four eight-bit words, each
defining one pixel of picture information, from the RAM 47 to the four
output buffers or registers 52 through 55 inclusive.
The controller switches "myslot" and counts and switches the first three
clock signals in succession to registers 52, 53, and 54. On each clock
pulse one eight-bit word is loaded in parallel into the register addressed
by that particular clock pulse. On the fourth clock pulse the controller
50 switches the data flow direction for register 55 to output and directs
loading of the fourth data word in that register in parallel. On that same
fourth clock pulse controller 50 sends the output enable signal to all
four registers and the four eight-bit data words are read out to the PC in
parallel over the thirty-two lines previously designated and shown in
FIGS. 3 (and 5). The controller also sends the "acknowledge" or "ready"
signal back to the PC over pin 28, which signal means that four-word data
transfer operation is complete and the invention is ready for the next
"myslot", at which time the data transfer sequence just described is
repeated until an entire frame is read out.
When the entire picture frame has been read out, controller 50 directs
storage in the RAM 47 of another frame. When the next frame is assembled,
the controller 50 notifies the PC (by sending NMRQ) that it is ready and
waits for the next "myslot". The signal flow and operation has been
previously described under the disclosure of the invention, with control
of internal operations being directed as previously described by the I2C
control system.
VERSION OF INVENTION FOR BLACK AND WHITE PICTURE
The invention comprises a plug-in computer card of the same characteristics
as previously described for the color version of the invention, and
general observations made there apply herein.
The invention has the capability of providing to a PC for display on its
screen a continuous black and white inset or overlay picture, as
controlled by the operator through the PC with software provided with the
invention. While the mode of processing is essentially unchanged, the
invention is available in two models providing different capabilities: the
MicroTV provides a display of 128.times.128 pixels; the DigiVideo version
has a switchable output to provide either 128.times.128 pixels or
256.times.256 pixels, depending upon the machine and software with which
it is used. This discussion is primarily addressed to use with the
Macintosh II series of computers.
The input connectors are as previously described for the color version, as
is the basic processing chain, except that it is simpler for a black and
white picture. The system elements are largely discrete circuits
available, with external networks of standard design to provide proper
functioning.
In summary, referring initially to FIG. 5, the MicroTV standard plug-in
card for the Macintosh II connects with the Macintosh internal processing
bus designated as the NuBus. The sequence of processing within the
invention includes the following steps:
1. The desired channel of TV reception may be selected by keyboard control,
or with the mouse, using software provided with the invention and
installed in the PC. The software provides for tuning the TV tuner by
voltage control oscillator, utilizing "look-up" tables for the control
frequency for each channel and for the voltage to the VCO to tune that
frequency, actual control of the tuner being through the I2C controller 64
(74LS378), using a clock line and a signal pulse line. The tuner is a
commercially available component, Samsung EBC-1731AL. The tuner or
alternate source signal is switched by a switching network 27, of discrete
circuitry of standard design. The audio signal included in the TV or other
source signal is received separately from the tuner or RCA pin-plug and is
routed to either an internal miniature speaker mounted on the card or to
the output pin plug mentioned above.
The audio speaker is a standard miniature, of which many are available.
Frequency control and stability are provided by the phase-locked-loop
design of the tuner utilized.
2. The video component is switched to a video signal conditioning circuit
36 (a combination of discrete circuitry and standard chips, comprising
essentially a low-pass filter limiting the signal which passes through to
that portion of the TV picture signal below 3.5 MHz). This signal
processor strips the signal of any components other than its luminance
(black and white) elements, to restrict the signal to the gray scale
section of the PC video card.
3. An analog-to-digital (A-D) converter 48 (MC10321) continuously converts
this processed analog signal to digital format. The encoded 8-bit digital
words (each representing one pixel of video display coded for the
necessary gray scale area signal from the PC video color card) are stored
temporarily in internal random access memory (RAM) 26 (43256-100), prior
to readout by the novel data output transfer section of the invention,
which functions in the black and white version precisely as previously
described for the color version, except that its control elements are less
flexible. In the smaller model of the invention, called the MicroTV, which
is capable of providing a 128.times.128 pixel array to the PC, this RAM
storage uses about half of a standard 32 kilobit (32K) matrix. The
DigiVideo model, which provides a 256.times.256 pixel array, uses two 32
kilobit matrices for storage.
Referring to FIG. 5, the invention's novel data transfer and control stage
for the black and white model, which was indicated as 60 in the system
block diagram FIG. 5, are shown to explain the control of this version of
the device, which functions exactly as described previously for the color
version. Also shown, designated 28, is the 92-pin connector which mates
the card to the Nu-bus in the Macintosh II PC. In FIG. 5, double lines
represent data transfer in parallel over eight lines for the eight-bit
words used to define picture pixels. The ultimate bit numbers for the
final 32-bit word transferred to the Macintosh II are indicated by the
corresponding pin numbers on connector 28 to which they are addressed, in
four-bit groups (AD0, AD4, etc, through AD28). Control signal flow is
shown in lighter lines.
The elements of this novel input-output control and data transfer device
are, in addition to a programmable array logic state machine or controller
31, a 2-bit counter 62 (74F163), a 2:4 demultiplexer 63 (74F139), three
uni-directional eight-bit latched data registers or buffers 52, 53, and 54
(74F534) and a bi-directional eight-bit register 55 (74F640). The logic
state machine 31 is part No. PAL 16R4, which is configured by having its
switches "burned" by a program, for which see below.
Communication of the invention with the PC is through connector 28. The
following signals are required for control and data transfer:
a signal called NMRQ (non-maskable interrupt data request), is sent by
controller 61 to the PC via pin 31 of connector 28, to inform the PC that
a complete picture frame is ready in the RAM for transfer;
the signal called "myslot" in Macintosh language, is received by the
invention on pin 92 and is routed to both the controller 61 and the 2 bit
counter 62;
the clock signal (every 100ns) is received on pin 96 to go to the
controller 61, and the 2-bit counter 62, it is also provided by the
controller to the RAM 49 for synchronization;
the "ready" or "acknowledge" is returned on pin 28;
address code and I2C control signals are received on the eight pins
designated which communicate with bi-directional buffer 55 (pin-pairs 82 &
18, 83 & 19, 84 & 20 and 85 & 21). The eight-pin data bus as designated on
FIG. 2 goes to the memory 26 and the I2C controller 64 shown in FIG. 4,
previously described.
On "myslot", controller 61 directs transfer of four eight-bit words, each
defining one pixel of picture information, from the RAM 49 to the four
output buffers or registers 52 through 55 inclusive.
Two-bit counter 62 receives "myslot", and then the four clock signals,
which it routes in succession to the 2:4 demultiplexer 63. The
demultiplexer counts and switches the first three clock signals in
succession to registers 52, 53 and 54. On each clock pulse one eight-bit
word is loaded in parallel into the register addressed by that particular
clock pulse. The fourth clock pulse is switched by the demultiplexer 63
back to the 2-bit counter 62, which turns off.
On that fourth clock pulse the controller 61 switches the data flow
direction for register 55 to output and directs loading of the fourth data
word in that register in parallel. On that same fourth clock pulse
controller 61 sends the output enable signal to all four registers and the
four eight-bit data words are read out to the PC in parallel over the
thirty-two lines previously designated and shown in FIG. 2. The controller
also sends the "acknowledge" or "ready" signal back to the PC over pin 28
of connector 28, which signal means that four-word data transfer operation
is complete and the invention is ready for the next "myslot", at which
time the data transfer sequence just described is repeated until an entire
frame is read out.
When the entire picture frame has been read out, controller 61 directs
storage in the RAM 49 of another frame. When the next frame is assembled,
the controller 61 notifies the PC (by sending NMRQ) that it is ready and
waits for the next "myslot".
The system output controller 61 is a programmable-array-logic (PAL) module,
configured to direct the sequence of operations described previously by a
PAL programmer in accordance with JEDEC code set forth immediately
following:
______________________________________
ABEL(tm) 3.10 Data I/O Corp. JEDEC file for: P16R4 V7.0
Created on: 8-Nov-89 08:38 AM
AAPPS MACTV
NuBus state control pal - - p/n MTV-1 Revision 1.0*
QP20* QF2048*
L0000
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11101111111111111111111101110111
11111111111011101101110101111111
11111111110111101110110101111110
00000000000000000000000000000000
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11111111111111111111111111111111
11111110111111111111111101110111
11111110111111101111111101111111
11111111110101100101010101111011
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11111111110111101110110101101111
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11111111110010101111110101101111
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00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
Aapps MicroTV & DigiVideo PAL Jedic Listing May 14, '90
00000000000000000000000000000000
11111111111111111111111111111111
11111111111111111111111101100111
11111111111111101111111101101111
11111111110110100101100101111011
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
11111111111111111111111111111111
11111111111111111111111101110110
11111111111111101111111101111110
11111111110101100101100101111011
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000*
C5067*
#B9FF
______________________________________
The above disclosure of my invention, including the special data transfer
circuit and its novel programmed control circuit, is considered the best
mode for carrying out its function. Minor variations are considered to be
within the scope and limits of the invention, as defined in the claims set
forth below.
##SPC1##
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