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United States Patent | 5,586,223 |
Bryant ,   et al. | December 17, 1996 |
A high speed, feed forward, segmented neural network and fabrication technique are described. The segmented network includes a plurality of network layers stacked in an ascending pyramid fashion. The network layers are structured with a plurality of subnetworks, and within each subnetwork exists a plurality of nodes structured in a fully interconnected and/or partially interconnected layered neural network arrangement. The inputs and outputs of each subnetwork are one bit digital values constrained to `0` or `1`, while any number of nodes with any number of layers may be modeled for each subnetwork. Each subnetwork is independent of all other subnetworks in a given network layer, and thus, each network layer is segmented. In hardware implementation, each subnetwork comprises a simple memory device, such as a RAM or PROM look-up table. The speed of the neural network system is high and largely dictated by the access time of the memory devices used.
Inventors: | Bryant; Steven M. (Holley, NY); Loewenthal; Kenneth H. (Rochester, NY) |
Assignee: | Eastman Kodak Company (Rochester, NY) |
Appl. No.: | 389550 |
Filed: | February 15, 1995 |
Current U.S. Class: | 706/41; 706/31 |
Intern'l Class: | G06F 015/80 |
Field of Search: | 395/27,24,21,22 |
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