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United States Patent | 5,579,322 |
Onodera | November 26, 1996 |
An object of the present invention is to provide an embedded testing circuit of a dual port memory capable of effectively testing the memory using a short test pattern while making simultaneous write/read from both of the ports. The testing circuit comprises an address inputting circuit selectively supplying M-sequence pattern data or their inverted pattern data to scan registers on the port A at the address input side and also selectively supplying pattern data in inverse relationship to the pattern data supplied to the port A to scan registers on the port B and a data inputting circuit selectively supplying the M-sequence pattern data or their inverted pattern data passed through the scan registers on the port A at the address input side to scan registers on the port A at the data input side and also selectively supplying the inverted pattern data or the M-sequence pattern data passed through the scan registers on the port B at the address input side to scan registers on the port B at the data input side.
Inventors: | Onodera; Takeshi (Kanagawa, JP) |
Assignee: | Sony Corporation (JP) |
Appl. No.: | 295439 |
Filed: | August 25, 1994 |
Sep 02, 1993[JP] | 5-243863 |
Current U.S. Class: | 714/730; 714/718; 714/720 |
Intern'l Class: | G01R 015/12; G11C 029/00 |
Field of Search: | 371/21.3,22.3,22.5,21.1,25 324/73 R,158 R 365/201 |
3961252 | Jun., 1976 | Eichelberger | 324/73. |
5040150 | Aug., 1991 | Naitoh et al. | 365/201. |
5222067 | Jun., 1993 | Hiroshi | 371/21. |
Conference Paper; Built-in Self Test in Multi-Post RAMS Castro, A. V.; Nicolaidis, M; Lestrat, P; Courtois, B. 1991 IEEE International Conference on Computer aided Design pp. 248-251. "Built-in self test for Multi-port Rams" by V. Castro Alves, M. Nicolaidis, P. Lestrat and B. Courtois. |