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United States Patent | 5,574,685 |
Hsu | November 12, 1996 |
An improved one-transistor flash EEPROM cell structure and a method for making the same is provided so that the effective channel length dimension is independent of the critical dimensions of the stacked gate structure. The cell structure (210) includes an n.sup.- buried channel/junction region (216) which is implanted in a substrate (212) before formation of a tunnel oxide (226) and a stacked gate structure (234). After the formation of the stacked gate structure, a p-type drain region (222) is implanted with a large tilt angle in the substrate. Thereafter, n.sup.+ source and n.sup.+ drain regions (218, 224) are implanted in the substrate so as to be self-aligned to the stacked gate structure. The cell structure of the present invention facilitates scalability to small size and is useful in high density application.
Inventors: | Hsu; James (Saratoga, CA) |
Assignee: | Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Appl. No.: | 299876 |
Filed: | September 1, 1994 |
Current U.S. Class: | 365/185.18; 257/316; 257/321; 257/339; 257/E21.422; 257/E29.306; 365/185.06; 365/185.11; 365/185.33 |
Intern'l Class: | G11C 016/04 |
Field of Search: | 365/185.01,185.06,185.11,185.33,185.18 257/321,316,339 |
4996571 | Feb., 1991 | Kume et al. | 365/185. |
5021848 | Jun., 1991 | Chiu | 257/321. |
5300802 | Apr., 1994 | Komori et al. | 257/316. |
5337274 | Aug., 1994 | Ohji | 365/185. |
5345104 | Sep., 1994 | Prall et al. | 257/316. |
5455790 | Oct., 1995 | Hart et al. | 365/185. |
5461249 | Oct., 1995 | Ozawa | 365/185. |
5464999 | Nov., 1995 | Bergemont | 365/185. |
5468981 | Nov., 1995 | Hsu | 257/316. |
5477072 | Dec., 1995 | Goo | 257/316. |