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United States Patent | 5,559,976 |
Song | September 24, 1996 |
A processing system and method of operation are provided. Multiple instructions are dispatched in a sequence to execution circuitry. Ones of the instructions are executed with the execution circuitry, and respective results are output in response thereto, Each executed instruction is completed in response to finishing execution of each instruction preceding the executed instruction in the sequence, independent of whether the results are stored in at least one storage location specified by the completed instructions.
Inventors: | Song; Seungyoon P. (Austin, TX) |
Assignee: | International Business Machines Corporation (Armonk, NY) |
Appl. No.: | 220998 |
Filed: | March 31, 1994 |
Current U.S. Class: | 712/215 |
Intern'l Class: | G06F 009/38 |
Field of Search: | 395/375 |
4858176 | Aug., 1989 | Wilhite et al. | 395/375. |
5051940 | Sep., 1991 | Vassiliadis et al. | 364/736. |
5077692 | Dec., 1991 | McMinn | 365/230. |
5129067 | Jul., 1992 | Johnson | 395/375. |
5136697 | Aug., 1992 | Johnson | 395/375. |
5177701 | Jan., 1993 | Iwasa | 364/736. |
5185872 | Feb., 1993 | Arnold et al. | 395/375. |
5197135 | Mar., 1993 | Eickemeyer et al. | 395/375. |
5202889 | Apr., 1993 | Aharon et al. | 371/27. |
5214763 | May., 1993 | Blaner et al. | 395/375. |
5222244 | Jun., 1993 | Carbine et al. | 395/800. |
5257214 | Oct., 1993 | Mason et al. | 364/736. |
5257216 | Oct., 1993 | Sweedler | 364/748. |
5261066 | Nov., 1993 | Jouppi et al. | 395/425. |
5268855 | Dec., 1993 | Mason et al. | 364/748. |
5274818 | Dec., 1993 | Vasilevsky et al. | 395/700. |
Popescu et al., "The Metaflow Architecture," IEEE Micro, Jun. 1991, pp. 10-13 and 63-73. IEEE Transacting on Computers, vol. 39, No. 3, Mar. 1990, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers" to G. S. Sohi, pp. 349-359. |