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United States Patent | 5,554,568 |
Wen | September 10, 1996 |
This invention describes a device structure and a method of forming the device structure using trenches with sidewalls formed in the substrate of an integrated circuit. A highly doped polysilicon layer is formed on the walls of the trench or the trench is filled with highly doped polysilicon to form the source and drain of a field effect transistor in an integrated circuit. The invention provides reduced source and drain resistance. The capacitances between the gate and source and the gate and drain are reduced as well.
Inventors: | Wen; Jemmy (Hsinchu, TW) |
Assignee: | United Microelectronics Corporation (Hsin-Chu, TW) |
Appl. No.: | 365047 |
Filed: | December 27, 1994 |
Current U.S. Class: | 438/197; 257/E21.431; 257/E21.619; 257/E29.021; 257/E29.04; 438/301 |
Intern'l Class: | H01L 021/44; H01L 021/48 |
Field of Search: | 437/29,40 DM,41 DM,913,203,52,40 DM 257/302,328,329,330,331,332,333,334,395,396,392,398,399 |
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4835584 | May., 1989 | Lancaster | 357/23. |
4963502 | Oct., 1990 | Teng et al. | 437/52. |
5111257 | May., 1992 | Andoh et al. | 257/397. |
5204280 | Apr., 1993 | Dhong et al. | 437/52. |
5293512 | Mar., 1994 | Wen | 257/622. |