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United States Patent | 5,539,786 |
Snelgrove | July 23, 1996 |
A digital circuit comprising a pair of D Flip-Flops which synchronize an oming NRZ.sub.-- L serial data stream to an external ten megahertz clock signal. The combination of a third D Flip-Flop and an EXCLUSIVE-NOR gate generates a clear pulse whenever a change of state occurs within the synchronized serial data stream. This clear pulse is supplied to a ten state state machine resetting the state machine to state S0. When the state machine transition to state S4 the state machine generates an enable signal which is supplied to a toggle Flip-Flop enabling the Flip-Flop allowing the Flip-Flop to change state. The ten megahertz clock signal then clocks the toggle Flip-Flop causing the Flip-Flop to change state. At state S9 the state machine again provides an enable signal to the toggle Flip-Flop enabling the toggle Flip-Flop which allows the ten megahertz clock signal to change the state of the output of the toggle Flip-Flop. This results in one megahertz clock signal at the output of the toggle Flip-Flop which is synchronized to the incoming serial data stream.
Inventors: | Snelgrove; Andrew H. (Ventura, CA) |
Assignee: | The United States of America as represented by the Secretary of the Navy (Washington, DC) |
Appl. No.: | 521385 |
Filed: | July 31, 1995 |
Current U.S. Class: | 375/373; 326/93; 326/96; 375/355 |
Intern'l Class: | H03D 003/24 |
Field of Search: | 375/371,373,362,363,364,354,355 327/141-142 326/93,96 331/14 |
3980820 | Sep., 1976 | Niemi et al. | 375/373. |
4716578 | Dec., 1987 | Wight | 375/354. |
5128970 | Jul., 1992 | Murphy | 375/354. |
5402453 | Mar., 1995 | Vavreck et al. | 375/373. |