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United States Patent |
5,537,112
|
Tsang
|
July 16, 1996
|
Method and apparatus for implementing run length limited codes in
partial response channels
Abstract
A method apparatus for encoding segments having a selected number of
ordered bits of binary data from a sequence of ordered bits of binary data
into corresponding codewords having a selected number of ordered bits of
binary data, such that the sequence of ordered bits of binary data is
encoded into a sequence of codewords. The apparatus comprises a receiver
device for receiving the segments; a separating device for separating the
selected number of ordered bits of binary data of each segment into a
corresponding first group and a corresponding second group; an encoder
mapping device for mapping each first group into a corresponding word
having a selected number of ordered bits of binary data; and an
interleaving device for interleaving the bits of each corresponding second
group with the selected number of ordered bits of binary data of each
corresponding word to obtain the corresponding codewords.
Inventors:
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Tsang; Kinhing P. (Plymouth, MN)
|
Assignee:
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Seagate Technology, Inc. (Scotts Valley, CA)
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Appl. No.:
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180567 |
Filed:
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January 12, 1994 |
Current U.S. Class: |
341/59; 341/61 |
Intern'l Class: |
H03M 007/00 |
Field of Search: |
341/59,61
|
References Cited
U.S. Patent Documents
4544962 | Oct., 1985 | Kato | 360/40.
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4707681 | Nov., 1987 | Eggenberger.
| |
Other References
Siegel et al., "Modulation and Coding For Information Storage", IEEE
Communications Magazine, Dec. 1991, pp. 68-86.
|
Primary Examiner: Gaffin; Jeffrey A.
Assistant Examiner: JeanPierre; Peguy
Attorney, Agent or Firm: Kinney & Lange
Claims
What is claimed is:
1. An apparatus for encoding segments having a selected number of ordered
bits of binary data, from a sequence of ordered bits of binary data into
corresponding codewords, having a selected number of ordered bits of
binary data, such that the sequence of ordered bits of binary data is
encoded into a corresponding sequence of codewords, the apparatus
comprising:
receiver means for receiving the segments;
separating means for separating the selected number of ordered bits of
binary data of each segment into a corresponding first group and a
corresponding second group;
encoder mapping means for mapping each first group into a corresponding
word having a selected number of ordered bits of binary data; and
interleaving means for interleaving the bits of each corresponding second
group with the selected number of ordered bits of binary data of each
corresponding word to obtain codewords corresponding to the segments, such
that (a) each codeword has no more than a first preselected number of
consecutive zeros therein, (b) adjacent codewords in the sequence of
codewords have no more than the first preselected number of consecutive
zeros across the boundary therebetween, (c) each codeword comprises two
subsequences, one subsequence consisting only of every other bit of the
selected number of ordered bits of binary data of the codeword and another
subsequence consisting only of the remaining bits with each of the
subsequences having no more than a second preselected number of
consecutive zeros therein, and (d) adjacent subsequences of codewords
within the sequence of codewords have no more that the second preselected
number of zeros across the boundary therebetween.
2. The apparatus as in claim 1, wherein the first and second preselected
number of consecutive zeros is six.
3. The apparatus as in claim 1, wherein the first preselected number of
consecutive zeros is eight and the second preselected number of zeros is
six.
4. The apparatus as in claim 1, wherein the ratio of the selected number of
bits of binary data in each segment to the selected number of ordered bits
of binary data in each corresponding codeword is 16/17.
5. The apparatus as in claim 1, wherein the selected number of bits of
binary data in the first and second groups is eight.
6. The apparatus as in claim 5, wherein the encoder mapping means maps the
first group of eight bits of binary data into words having nine bits of
binary data.
7. The apparatus as in claim 1, wherein the selected number of bits in the
first group is nine and wherein the selected number of bits in the second
group is seven.
8. The apparatus as in claim 7, wherein the encoder mapping means maps the
first group of nine bits of binary data into words having ten bits of
binary data.
9. The apparatus as in claim 1, further comprising decoder means for
decoding a selected number of codewords into a selected number of bits of
binary data.
10. The apparatus as in claim 9, wherein the decoder means comprises:
receiver means for receiving the sequence of codewords;
decoder separating means for separating the selected number of ordered bits
of binary data of each codeword back into the corresponding word and into
the second group; and
decoder mapping means for mapping each corresponding word back into the
first group; such that the corresponding segment is formed.
11. A method for encoding a segments having a selected number of ordered
bits of binary data, from a sequence of ordered bits of binary data into
corresponding codewords, having a selected number of ordered bits of
binary data, such that the sequence of ordered bits of binary data is
encoded into a sequence of codewords, the method comprising:
receiving the segments;
separating the selected number of ordered bits of binary data of each
segment into a corresponding first group and a corresponding second group;
mapping each first group into a corresponding word having a selected number
of ordered bits of binary data; and
interleaving the bits of each corresponding second group with the selected
number of ordered bits of binary data of each corresponding word to obtain
codewords corresponding to the segments, such that (a) each codeword has
no more than a first preselected number of consecutive zeros therein, (b)
adjacent codewords in the sequence of codewords have no more than the
first preselected number of consecutive zeros therebetween, (c) each
codeword comprises two subsequences, one subsequence consisting only of
every other bit of the selected number of ordered bits of binary data of
the codeword and another subsequence consisting only of the remaining bits
with each of the subsequences having no more than a second preselected
number of consecutive zeros therein, and (d) adjacent subsequences of
codewords within the sequence of codewords have no more that the second
preselected number of zeros across the boundary therebetween.
12. The method as in claim 11, wherein the first and second preselected
number of consecutive zeros is six.
13. The method as in claim 11, wherein the first preselected number of
consecutive zeros is eight and the second preselected number of zeros is
six.
14. The method as in claim 11, wherein the ratio of the selected number of
bits of binary data of each segment to the selected number of ordered bits
of binary data in each codeword is 16/17.
15. The method as in claim 11, wherein the selected number of bits of
binary data in the first and second groups is eight.
16. The method as in claim 15, wherein the first group of eight bits of
binary data is mapped into words having nine bits of binary data.
17. The method as in claim 11, wherein the selected number of bits in the
first group is nine and wherein the selected number of bits in the second
group is seven.
18. The method as in claim 17, wherein the first group of nine bits of
binary data is mapped into words having ten bits of binary data.
19. The method as in claim 11, further comprising the step of decoding a
selected number of codewords into a selected number of bits of binary
data.
20. The method as in claim 19, wherein the step of decoding further
comprises:
receiving the sequence of codewords;
separating the selected number of ordered bits of binary data of each
codeword back into the word having a selected number of ordered bits of
binary data and back into the second group of the selected number of bits
of binary data; and
mapping the first group of selected the word back into the first group of
the selected number of bits of binary data.
Description
BACKGROUND OF THE INVENTION
The present invention relates in general to information storage systems,
and more particularly, to a method and apparatus for implementing run
length limited codes in partial response channels in a digital magnetic
recording system.
In digital magnetic recording systems, data is recorded in a moving
magnetic media layer by a storage, or "write" electrical
current-to-magnetic field transducer, or "head", positioned immediately
adjacent thereto. The data is stored or written to the magnetic media by
switching the direction of flow of a substantially constant magnitude
write current which flows through windings in the write transducer. Each
write current direction transition results in a reversal of the
magnetization direction in that portion of the magnetic media just passing
by the transducer during current flow in the new direction, with respect
to the magnetization direction in the media induced by the previous
current flow in the opposite direction. In one scheme, a magnetization
direction reversal over a portion of the media moving past the transducer
represents a binary digit "1", and the lack of any reversal in that
portion represents a binary digit "0".
When data is to be recovered, a retrieval, or "read" magnetic
field-to-voltage transducer, (which may be the same as the write
transducer if both are inductive) is positioned to have the magnetic
media, containing previously stored data, pass thereby such that flux
reversal regions in that media either induce, or change a circuit
parameter to provide, a voltage pulse to form an output read signal for
that transducer. In the scheme described above, each such voltage pulse
due to the magnetizations in corresponding media portions represents a
binary digit "1" and the absence of a pulse in correspondence with such
portions represents a binary digit "0".
In digital magnetic recording systems using peak detection of such voltage
pulses as the data recovery method to digitize the read signal, the times
between voltage pulses are used to reconstruct the timing information used
in recording the data previously stored in the magnetic media to define
the path portions described above. More specifically, the output of such a
peak detector is used as an input signal to a phase-locked loop forming a
controlled oscillator, or phase-lock oscillator (PLO), or synchronizer,
which produces an output clock signal from the positions of the detected
peaks of the read signal. Absolute time is not used in operating the data
retrieval system portion since the speed of the magnetic media varies over
time which results in nonuniform time intervals between read signal
voltage pulses.
A data encoding scheme known as run-length-limited (RLL) coding is commonly
used to improve the PLO's reconstructed clock signal accuracy based on
avoiding drift in the frequency thereof because of too much time between
voltage read signal pulses. When RLL code is employed, the time durations
between read signal voltage pulse transitions is bounded, that is, the
number of binary digits of value "0" that can separate binary digits of
value "1" in the read signal is limited. This constraint is known overall
as a (d,k) constraint where the individual constraint "d" represents the
minimum run length of zeros, or the number thereof between ones, while the
individual constraint "k" represents the maximum run length of zeros
permitted. The "d" portion of the constraint can be chosen so as to avoid
crowding of voltage pulses in the read signals which can reduce
intersymbol interference problems in which portions of read signal voltage
pulses overlap. By limiting the number of consecutive zeros, the "k"
constraint maintains the reliability of the PLO in providing an accurate
clock signal for the retrieval system. An automatic gain control (AGC)
system is used to maintain signal amplitude for the PR4 channel, and the
"k" restraint also maintains the reliability of the AGC.
In digital magnetic recording systems employing partial response (PR)
signaling, which involves the acceptance of intersymbol interference, data
recovery is achieved by periodically sampling the amplitude of the read
transducer output signal, as initiated by clock pulses of the PLO, to
digitize that signal. In this scheme, each clock pulse of the PLO
initiates a sample which has value contributed to it by more than one
pulse in the transducer read signal. Thus, a partial response detection
system is designed to accommodate the effects of such intersymbol
interference, and therefore the "d" constraint may not be necessary (i.e.
d=0). The "k" constraint is still necessary in PR signalling because the
PLO is still used to provide timing for sampling the read signal, and
because the AGC is used to maintain sample amplitude in connection with
the PR channel.
A selected frequency response is chosen for the signal channel through
which the read signal passes prior to detection thereof, termed a class 4
response, that is particularly suitable for magnetic recording with
typical pulse characteristics because the channel requires very little
equalization to achieve an overall match of this class 4 response. In a
class 4 PR channel for typical pulse characteristics, signal samples are
independent of their immediately neighboring samples, but are dependent on
samples 2 clock samples away. Therefore, read samples can be divided into
2 subsequences, one of odd indexed samples and one of even indexed
samples. Each such subsequence is submitted independently to a Viterbi
Algorithm decoder which generates the data that most likely reproduces the
original stored values. To limit the delay and increase the accuracy and
reliability of the Viterbi Algorithm decoder, another individual
constraint, "i", is incorporated in the RLL code for a class 4 partial
response channel. The "i" constraint represents the maximum run length of
zeros in each subsequence, and the overall constraint for a class 4 PR
channel is denoted as (d, k/i), where "d" and "k" represent the same
constraints as mentioned above with respect to (d,k) code, and where "d"
is set to zero as indicated above.
In order to satisfy the (d, k/i) constraint, "m" data symbols or bits are
mapped into "n" code symbols, where "m" is less than "n". The rate of the
code to transmit information bits out of the total bits transmitted is
given by the formula r=m/n, and for ease of implementation "m" and "n" are
usually chosen to be small integers. Since a unit of 8 bits per byte is
widely used in the computer and electronic industry, reasonable choices of
"m" are 8 and 16. In order to keep the code rate high, "n" is chosen to be
equal to "m+1" and so code rates of 8/9 and 16/17 are popular for class 4
partial response channels.
The "m" data symbols, or binary data bits are mapped into the "n" code
symbols, or binary data bits, by selecting 2.sup.m different n-bit
patterns which satisfy the (d, k/i) constant. Since Boolean logic is used
to implement such bit pattern mapping, the larger the "m" and "n" are, the
more complex the Boolean logic that is required. In recent years the 8/9
rate for such run length codes has been the most popular rate since it
only requires 2.sup.8 or 256 different 9-bit patterns which satisfy the
(0, k/i) constraint which simplifies the encoder and decoder Boolean logic
required to implement the pattern mapping. However, the 16/17 rate in such
codes is 5.8% higher than the 8/9 rate for encoding a given set of data.
In order to develop a rate of 16/17 for a (0, k/i) RLL code using such bit
pattern mapping to encode the data symbols, there is needed 2.sup.16 or
65,536 17-bit patterns which must satisfy the (0, k/i) constraint. This
large number of possible 17-bit codeword combinations requires very
complex, and thus undesirable, encoder and decoder logic, compared to the
rate 8/9 RLL code. Thus, it would be desirable to provide a 16/17 rate RLL
code which is easier to implement than one otherwise obtained through
pattern mapping 2.sup.16 possible 17-bit code symbol or codeword
combinations.
SUMMARY OF THE INVENTION
The present invention relates to a method and apparatus for implementing
run length limited codes for partial response channels employing maximum
likelihood detection. The present invention relates to an apparatus for
encoding data segments having therein a selected number of ordered bits of
binary data obtained from a sequence of ordered bits of binary data. These
data segments are encoded into corresponding codewords having a selected
number of ordered bits of binary data such that the sequence of ordered
bits of binary data is encoded into a corresponding sequence of codewords.
The apparatus comprises receiver means for receiving the data segments,
separating means for separating the selected number of ordered bits of
binary data of each segment into a corresponding first group and a
corresponding second group, encoder mapping means for mapping the first
group into a corresponding word having a selected number of ordered bits
of binary data, and interleaving means for interleaving the bit of each
corresponding second group with the selected number of ordered bits of
binary data of each corresponding word to obtain the corresponding
codewords. Each such codeword has no more than a first pre-selected number
of consecutive zeros therein. Adjacent ones of these codewords in the
sequence of codewords have no more than the first pre-selected number of
consecutive zeros bridging across the boundary between them. Each such
codeword comprises two subsequences, one of these subsequence consisting
only of every other bit of the selected number of ordered bits of binary
data of the codeword and the other subsequence consisting only of the
remaining bits. Each of the subsequences has no more than a second
pre-selected number of consecutive zeros therein. Adjacent ones of these
subsequences of codewords within the sequence of codewords have no more
than the second pre-selected number of zeros bridging across the boundary
between them.
Run length limited codes under the present invention are suitable for
partial response channels for which Viterbi detection is employed in
decoding transmissions therethrough, and which are characterized by d, k,
and i constraints. According to the present invention, the alternative
overall constraints provided for a RLL code having a 16/17 rate are (0,
8/6) and (0, 6/6). The present invention is characterized by sequential
Boolean logic equations and look-up tables for encoding and decoding 16/17
rate RLL codes having these constraints. Although the present invention is
particularly related to partial response maximum likelihood detection code
constraints for use in magnetic recording of digital data in disc memory
devices, the code constraints and the equations for encoding and decoding
data in accordance herewith are applicable to any PR signalling system
including magnetic-optic and optical recording systems.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a system employing a 16/17 rate RLL code
modulation scheme under a (0, 8/6) constraint in accordance with the
principals of the present invention;
FIG. 2 is a table of 256 hexadecimal numbers equivalent to 9-bit binary
sequences for 8/9 rate RLL code for use in deriving a 16/17 rate RLL code
under a (0, 8/6) constraint in accordance with the principals of the
present invention;
FIG. 3 is a diagram of the table of FIG. 2 showing a partition grouping
pattern for a 16/17 rate RLL code under a (0, 8/6) constraint;
FIG. 4 is a block diagram of a system employing a 16/17 rate RLL code
modulation scheme under a (0, 6/6) constraint in accordance with the
principals of the present invention;
FIGS. 5A and 5B are tables of 512 hexadecimal numbers equivalent to 10-bit
binary sequences for 9/10 rate RLL code for use in deriving a 16/17 rate
RLL code under a (0, 6/6) constraint in accordance with the principals of
the present invention; and
FIG. 6 is a diagram of the table of FIG. 4 showing a partition grouping
pattern for a 16/17 rate RLL code under a (0, 6/6) constraint.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, a magnetic recording storage and retrieval system 10
utilizes a 16/17 rate RLL code scheme for writing bits of coded binary
data to magnetic media in system 10 from a binary data stream received
from a storage using system (not shown), system 10 thereafter permitting
selective reading of such data therefrom. The original sequence binary
data is considered as groups of 16 bits of data, such a group being
denoted D.sub.16 in FIG. 1, and the encoded data is represented by a
corresponding group of 17 bits of data denoted D.sub.17 in that figure.
System 10 includes an encoder 14 for receiving and encoding the groups of
ordered bits of binary data into corresponding codewords, a precoder 16,
having a 1/(1.sym.D.sup.2) transfer function suitable for use with a class
4 partial response (PR 4) read signal channel to aid in the subsequent
decoding of the data sent therethrough. This partial response read signal
channel is formed by the magnetic media, the heads used for reading and
writing the encoded data to and from the media (the media and head
together form a structure denoted by the reference number 18) and an
equalizer 20. The PR4 signal channel, if formed by head structure 18 and
equalizer 20, has the desired 1-D.sup.2 class 4 response. A Viterbi
algorithm detector 22 determines, from the read signal provided by the
read head in media and head structure 18, the most likely sequence of
recorded data codewords which produced that read signal. These results are
provided to a decoder 24 for receiving and decoding the sequences of
codewords to obtain the original ordered bits of binary data.
In accordance with the present invention, an RLL code having a 16/17 rate
and a (0, 8/6) overall (d,k/i) constraint is derived from an RLL code
having an 8/9 rate as will be explained below, to provide a simpler way of
encoding and decoding received data into a 16/17 rate RLL code than by
mapping the data groups received into corresponding ones of 2.sup.16
different 17-bit codeword patterns. The encoder 14 includes an input latch
30, an 8/9 encoder 32, an output latch 34, and a parallel-to-series
converter 36. A sequence of binary data bits from some system making use
of recording system 10, which data may have been previously encoded for
other purposes, is supplied to input latch 30 in encoder 14. These data
bits are synchronously entered therein 8 bits (1 byte) of binary data at a
time by a clocking signal supplied from an electronic clock oscillator
(not shown) based on a phase-lock loop provided elsewhere in system 10 as
described above. After 16 bits (two bytes) of binary have been clocked
into input latch 30, the 16 bits of binary data are treated as being
grouped into a first group of 8 bits, here denoted byte A, and a second
group of 8 bits, here denoted byte B, wherein:
A.DELTA.[A.sub.7, A.sub.6, A.sub.5, A.sub.4, A.sub.3, A.sub.2, A.sub.1,
A.sub.0 ], (1)
B.DELTA.[B.sub.7, B.sub.6, B.sub.5, B.sub.4, B.sub.3, B.sub.2, B.sub.1,
B.sub.0 ]. (2)
The logic gates in 8/9 encoder 32 perform certain logic functions (given
below) on byte A that effectively "maps" byte A into a 9-bit initial
codeword, C, wherein:
C.DELTA.[C.sub.8, C.sub.7, C.sub.6, C.sub.5, C.sub.4, C.sub.3, C.sub.2,
C.sub.1, C.sub.0 ], (3)
following the requirements for the selected run length constraint (0,8/6).
Output latch 34 interleaves 9-bit word C with byte B to form a 17-bit
codeword, W, which satisfies the (0, 8/6) overall constraint and which is
denoted as:
W.DELTA.[C.sub.8, B.sub.7, C.sub.7, B.sub.6, C.sub.6, C.sub.5, B.sub.5,
C.sub.4, B.sub.4, B.sub.3, B.sub.2, C.sub.3, B.sub.1, C.sub.2, C.sub.1,
B.sub.0, C.sub.0 ]. (4)
Parallel-to-series converter 36 serially provides the 17 bits of the
codeword W to the precoder 16 which, in turn, provides a further coded
version of them to the media portion of media and head structure 18.
The encoded data (codewords W) can thereafter be selectively read as
desired from this media to form a read signal which passes through the
rest of the PR 4 signal channel, as maintained by equalizer 20, to reach
Viterbi algorithm detector 22. Precoder 16, media and head structure 18,
equalizer 20, Viterbi algorithm detector 22, input latch 30, output latch
34 and parallel-to-serial converter 36 are well known components to those
skilled in the art. Those skilled in the art will recognize that there are
many ways to configure digital magnetic recording system 10, but the
present invention is directed to the encoding scheme established by the
logic structure of encoder 14 which uses a relatively simple technique to
provide RLL coding of incoming data at an information symbol rate of 16/17
through interleaving the 9 code bits of word C with the data bits of byte
B to form codeword W.
Each codeword W includes two subsequences of alternating bits, wherein a
first subsequence, W.sub.1, consists only of every other bit in a codeword
W, and the second subsequence, W.sub.2, consists of the remaining bits of
that codeword W. Typically, the first subsequence, W.sub.1, is denoted as
an odd sequence because of having therein the bits from the odd numbered
bit positions in codeword W wherein:
W.sub.1 .DELTA.[C.sub.8, C.sub.7, C.sub.6, B.sub.5, B.sub.4, B.sub.2,
B.sub.1, C.sub.1, C.sub.0 ]. (5)
The remaining bits form the second sequence, W.sub.2, which is typically
denoted as an even sequence wherein:
W.sub.2 .DELTA.[B.sub.7, B.sub.6, C.sub.5, C.sub.4, B.sub.3, C.sub.3,
C.sub.2, B.sub.0 ]. (6)
It is necessary for proper operation of the system phase-lock loop, as
described above, to ensure that within each codeword W, and across the
boundary between adjacent codewords W in a sequence thereof, the maximum
number of consecutive zeros is 8. Similarly, within each subsequence
W.sub.1 and W.sub.2 and (a) across the boundary between adjacent
subsequences W.sub.1 in a sequence thereof, and (b) across the boundary
between adjacent subsequences W.sub.2 in a sequence thereof, the maximum
number of consecutive zeros is 6. Also, it is undesirable to constrain the
bits of byte B (which would effectively place a constraint on the user
system since byte B is not being encoded). Thus, the structure of 8/9
encoder 32 must effectively map byte A into codeword C so, in the worst
case scenario (when byte B is all zeros), the codeword W will still
satisfy the (0,8/6) constraint mentioned above. Since d=0, the following
conditions ensure that the "k" and "i" limits in this constraint are
satisfied:
C.sub.8 +C.sub.7 +C.sub.6 =1 (7)
C.sub.1 +C.sub.0 =1 (8)
C.sub.7 +C.sub.6 +C.sub.5 +C.sub.4 =1 (9)
C.sub.6 +C.sub.5 +C.sub.4 +C.sub.3 =1 (10)
C.sub.5 +C.sub.4 +C.sub.3 +C.sub.2 =1 (11)
C.sub.4 +C.sub.3 +C.sub.2 +C.sub.1 =1 (12)
C.sub.7 +C.sub.6 +C.sub.1 =1 (13)
C.sub.4 +C.sub.3 +(C.sub.5 .multidot.C.sub.2)=1 (14)
Equations 7 and 8 above ensure that the k=8 constraint is satisfied at the
boundary between adjacent codewords W since a 1 value for any of bits
C.sub.8, C.sub.7, and C.sub.6, and bits C.sub.1, and C.sub.0 of any
codeword W.sub.n (see equation 4 above) effectively limits the length of a
string of zeros possible over any 8 consecutive bits (assuming the worse
case scenario where byte B is all zeros) across the boundary between
codeword W and either of adjacent codewords W.sub.n.+-.1. Equations 9-12
ensure that within each codeword W the k=8 constraint is satisfied, since
a 1 value for any of bits C.sub.7, C.sub.6, C.sub.s, C.sub.4, C.sub.3,
C.sub.2 and C.sub.1 of codeword W (again see equation 4 above) effectively
limits the length of a string of zeros possible over any 8 consecutive
bits (assuming the worst scenario where byte B is all zeros) within each
codeword W. Equation 13, in combination with equations 7 and 8, ensures
that within each odd subsequence W.sub.1, and at the boundary between odd
subsequences W.sub.1 of codewords adjacent to W, the i=6 constraint is
satisfied, since a 1 value for any of bits C.sub.8, C.sub.7, C.sub.6,
C.sub.1 and C.sub.0 of codeword W effectively limits the length of a
string of zeros possible over any 6 consecutive bits within any odd
subsequence W.sub.1:n and over any 6 consecutive bits across the boundary
between odd subsequence W.sub.1:n and either of adjacent odd subsequences
W.sub.1n.+-.1. Equation 14, in combination with equations 1 and 2, ensures
that within each even subsequence W.sub.2, and at the boundary between
even subsequences W.sub.2 of codewords adjacent to W, the i=6 constraint
is satisfied, since a 1 value for any of bits C.sub.8, C.sub.7, C.sub.6,
C.sub.5, C.sub.4, C.sub.3, C.sub.2, C.sub.1 and C.sub.0 of codeword W
effectively limit the length of a string of zeros possible over any 6
consecutive bits within any even subsequence W.sub.2:n, and over any 6
consecutive bits across the boundary between each even subsequence
W.sub.2:n and either of adjacent even subsequences W.sub.2:n.+-.1.
There are 256 different 9-bit patterns which satisfy the conditions in
equations 7-14 which exactly matches the number of all possible 8-bit
patterns (i.e. 2.sup.8). FIG. 2 shows a table representing a one-to-one
mapping of any possible value of a byte A, taken as a two-digit
hexadecimal number, into the corresponding 9-bit word C taken as a three
digit hexadecimal number such that equations 7-14 are satisfied. The bit
patterns are shown in hexadecimal form in FIG. 2 for simplicity with the
least significant (LS) digit in the byte A hexadecimal number represented
in the top line and the most significant (MS) digit represented in the
leftmost column of the table of FIG. 2. Thus, 8/9 encoder 32 effectively
converts a value of byte A, represented by a digit in the top row and one
in the leftmost column of the table in FIG. 2, to the corresponding C word
value at the corresponding row and column interaction.
In order to simplify the implementation of the Boolean logic equations of
8/9 encoder 32 based on the table of FIG. 2, the 256 different values for
9-bit initial codeword C shown in the table of FIG. 2 can be grouped by
various partitioning schemes, including being grouped into the six
partitions thereof shown in FIG. 3. In other words, FIG. 3 is a diagram of
the table of FIG. 2 in which the various partitions, denoted by one of the
capital letters G, H, J, K, L and M, represent groups of 9-bit C words in
Table 2 having a predetermined relationship to each other described below.
All of the definitions of logic structure of 8/9 encoder 32 can be
expressed in Boolean logic expressions, wherein ".multidot." denotes an
AND gate, "+" denotes an OR gate, .sym. denotes an exclusive OR gate, and
" " denotes a NOT gate or logic invertor.
Referring to FIG. 3, the first partition of word assignments, denoted G,
comprises the set of data bytes correspondingly shown in FIG. 2 in which
the first and last 4 bits of the 8-bit binary data byte A are mapped
without change into the first and last 4 bits, respectively, of the 9-bit
word C. The middle bit, i.e. the 5th bit position, of the 9-bit word C in
this partition is always 1. Partition G comprises 8 groups of 18 different
9-bit words C as shown in FIG. 3, which total 144 separate C words and
which can be identified by the equation:
G=(A.sub.6 +A.sub.5).multidot.(A.sub.1 +A.sub.0). (15)
A second partition, H, comprises 8 groups of 6 different 9-bit C words as
shown in FIG. 3, which total 48 separate C words, which can be identified
by the equation:
H=(A.sub.6 .multidot.A.sub.5).multidot.(A.sub.1 +A.sub.0). (16)
A third partition, J, comprises 8 groups of 3 different 9-bit C words as
shown in FIG. 3, which total 24 separate C words, and which can be
identified by the equation:
J=(A.sub.5 +A.sub.4).multidot.(A.sub.2 .multidot.A.sub.i
.multidot.A.sub.0).(17)
A fourth partition, K, comprises 6 groups of 3 different 9-bits C words as
shown in FIG. 3, which total 18 separate C words and which can be
identified by the equation:
K=(A.sub.5 +A.sub.4).multidot.[(A.sub.3 .multidot.A.sub.2 .multidot.A.sub.1
.multidot.A.sub.0)+(A.sub.6 .multidot.A.sub.3 .multidot.A.sub.2
.multidot.A.sub.1 .multidot.A.sub.0)]. (18)
A fifth partition, L, comprises 16 individual C words as shown in FIG. 3,
which can be identified by the equation:
L=(A.sub.5 .multidot.A.sub.4).multidot.(A.sub.1 .multidot.A.sub.0).(19)
A sixth partition, M, comprises the remaining 2 groups of 3 9-bit words C,
as shown in FIG. 3, which total 6 separate C words and which can be
identified by the equation:
M=A.sub.6 .multidot.(A.sub.5 +A.sub.4).multidot.(A.sub.3 .multidot.A.sub.2
.multidot.A.sub.1 .multidot.A.sub.0). (20)
The Boolean logic equations for 8/9 encoder 32 for encoding data bits
A.sub.7 -A.sub.0 into codeword bits C.sub.8 -C.sub.0 based on the table of
FIG. 2 are simplified using these partitions, and so the following
equations for this encoder are presented utilizing the six partitions
equations G, H, J, K, L and M described above in equations 15-20:
C.sub.8 =G.multidot.A.sub.7 +H.multidot.A.sub.7 +J.multidot.A.sub.7
+K.multidot.A.sub.7 +L+M (21)
C.sub.7 =G.multidot.A.sub.6 +H.multidot.A.sub.4 +J+K.multidot.(A.sub.6
+A.sub.3) (22)
C.sub.6 =G.multidot.A.sub.5 +H.multidot.A.sub.4 +J+K.multidot.A.sub.6(23)
C.sub.5 =G.multidot.A.sub.4 +H.multidot.A.sub.3 +J.multidot.A.sub.3
+K+L.multidot.A.sub.7 +M (24)
C.sub.4 =G+L.multidot.(A.sub.7 +A.sub.6)+M.multidot.(A.sub.7 +A.sub.5)(25)
C.sub.3 =G.multidot.A.sub.3 +H+J+L.multidot.(A.sub.7
.sym.A.sub.6)+M.multidot.(A.sub.7 +A.sub.5) (26)
C.sub.2 =G.multidot.A.sub.2 +H.multidot.A.sub.2 +J.multidot.A.sub.6
+K+L.multidot.A.sub.3 +M.multidot.A.sub.5 (27)
C.sub.1 =G.multidot.A.sub.1 +H.multidot.A.sub.1 +J.multidot.A.sub.5
+K.multidot.A.sub.5 +L+M (28)
C.sub.0 =G.multidot.A.sub.0 +H.multidot.A.sub.0 +J.multidot.A.sub.4
+K.multidot.A.sub.4 +L.multidot.A.sub.2 +M.multidot.(A.sub.4
.multidot.(A.sub.7 +A.sub.5)) (29)
Those skilled in the art will recognize that other partitions are possible,
that Boolean expressions further reduced, or other equivalent expressions
perhaps more conducive to implementing the particular logic gate circuits
chosen for use, may be obtained for the present logic expressions
described in equations 15-29, and thus, that there are other possible
forms for the logic equations (equations 15-29) used in constructing 8/9
encoder 32. As mentioned above, the 9 bits of word C are interleaved with
the 8 bits of byte B to form the 17-bit codeword W which is written to and
read from the magnetic media in media and head structure 18.
Referring back to FIG. 1, decoder 24 functions to reconstruct the original
data bits A.sub.7 -A.sub.0 and B.sub.7 -B.sub.0 from the codeword W signal
read from the media in media and structure 18, after this signal is
transmitted over the equalized channel to reach Viterbi detector 22.
Decoder 24 includes serial parallel converter 50, input latch 52, 9/8
decoder 54, and output latch 56. Input latch 52 separates the interleaved
17 bits of codeword W into 9-bit word C and byte B. Here, 9/8 decoder 54
effectively converts a value of word C represented in a row-column
intersection of the table in FIG. 2 to the corresponding value of byte A
represented in the corresponding top row digit position and leftmost
column digit position. In doing so, 9/8 decoder 54 identifies six
partition groupings G, H, J, K, L and M similar to those used in the 8/9
encoder 32 (See FIG. 3 in terms of the location and number of the 9-bit
words C in each partition). Each partition group in 9/8 decoder 54 can be
expressed as a function of code bits C.sub.8 -C.sub.0 as follows:
G=C.sub.4 .multidot.(C.sub.7 +C.sub.6).multidot.(C.sub.1 +C.sub.0)(30)
H=C.sub.4 .multidot.(C.sub.7 .sym.C.sub.6).multidot.C.sub.3
.multidot.(C.sub.1 +C.sub.0) (31)
J=(C.sub.7 .multidot.C.sub.6 .multidot.C.sub.4).multidot.C.sub.3
.multidot.(C.sub.1 +C.sub.0) (32)
K=(C.sub.7 +C.sub.6).multidot.C.sub.5 .multidot.C.sub.4 .multidot.C.sub.3
.multidot.C.sub.2 .multidot.(C.sub.1 +C.sub.0) (33)
L=[C.sub.8 .multidot.C.sub.7 .multidot.C.sub.6 .multidot.(C.sub.5
.sym.C.sub.4).multidot.C.sub.3 .multidot.C.sub.1 ]+(C.sub.8
.multidot.C.sub.7 .multidot.C.sub.6 .multidot.C.sub.4 .multidot.C.sub.3
.multidot.C.sub.1) (34)
M=C.sub.8 .multidot.C.sub.7 .multidot.C.sub.6 .multidot.C.sub.5
.multidot.C.sub.1 .multidot.[(C.sub.4 .multidot.C.sub.3
.multidot.C.sub.2)+(C.sub.4 .multidot.C.sub.3)] (35)
The Boolean logic equations for 9/8 decoder 54 for decoding code bits
C.sub.8 -C.sub.0 into data bits A.sub.7 -A.sub.0 are given by the
following equations utilizing the six partition equations G, H, J, K, L
and M described above in equations 30-35:
A.sub.7 =G.multidot.C.sub.8 +H.multidot.C.sub.8 +J.multidot.C.sub.8
+K.multidot.C.sub.8 +L.multidot.C.sub.5 +M.multidot.C.sub.4
.multidot.(C.sub.2 +C.sub.0) (36)
A.sub.6 =G.multidot.C.sub.7 +J.multidot.C.sub.2 +K.multidot.(C.sub.7
.multidot.C.sub.6)+L.multidot.C.sub.4 .multidot.(C.sub.5 +C.sub.3)+M(37)
A.sub.5 =G.multidot.C.sub.6 +J.multidot.C.sub.1 +K.multidot.C.sub.1
+M.multidot.C.sub.2 (38)
A.sub.4 =G.multidot.C.sub.5 +H.multidot.C.sub.7 +J.multidot.C.sub.0
+K.multidot.C.sub.0 +M.multidot.(C.sub.0 +C.sub.2) (39)
A.sub.3 =G.multidot.C.sub.3 +H.multidot.C.sub.5 +J.multidot.C.sub.5
+K.multidot.(C.sub.7 .multidot.C.sub.6)+L.multidot.C.sub.2 +M(40)
A.sub.2 =G.multidot.C.sub.2 +H.multidot.C.sub.2 +K+L.multidot.C.sub.0
+M(41)
A.sub.1 =G.multidot.C.sub.1 +H.multidot.C.sub.1 (42)
A.sub.0 =G.multidot.C.sub.0 +H.multidot.C.sub.0 (43)
Output latch 56 provides as an output the original data bits A.sub.7
-A.sub.0 which were decoded by 9/8 decoder 54, and the data bits B.sub.7
-B.sub.0 which were recovered in input latch 52. Those skilled in the art
will recognize that further reductions in the Boolean expressions, or
other equivalent expressions more helpful in implementing the logic gate
circuits chosen, may be obtained for the present logic expressions
described in equations 30-43, and thus, that there are other possible
forms for the logic equations (equations 30-43) used for constructing 9/8
decoder gating 54.
In accordance with another embodiment of the present invention, as
illustrated in FIGS. 4-6, there is provided a system 10' utilizing an RLL
code having a 16/17 rate and (0, 6/6) overall (d, k, i) constraint which
is derived from an RLL code having a 9/10 rate as will be explained below,
to provide another way of encoding and decoding received data into a 16/17
RLL rate code again by the method of bit pattern mapping. This rate code
has a smaller "k" constraint, compared to the previously described 16/17
rate RLL code with a (0, 8/6) constraint, and is likely to increase update
information to the PLO and ACG to thereby provide better performance by
system 10', as compared to system 10. Unless otherwise stated, the
components hereinafter described with respect to the embodiment
illustrated in FIGS. 4-6 are the same as and will operate in the same
manner as those components described above with respect to the embodiment
illustrated in FIGS. 1-3. Components in FIGS. 4-6 which differ from
corresponding ones in FIGS. 1-3 are designated with the same number in
FIGS. 4-6 but with a prime symbol placed thereafter. Referring to FIGS.
4-6, encoder 14' is supplied with 16 binary data bit groups as before
which are then synchronously entered in latch 30' by the clocking signal
where they are treated as being in a first word having 9 bits therein,
here denoted A, and a second word having 7 bits therein, here denoted B,
wherein:
A.DELTA.[A.sub.8, A.sub.7, A.sub.6, A.sub.5, A.sub.4, A.sub.3, A.sub.2,
A.sub.1, A.sub.0 ], (44)
B.DELTA.[B.sub.6, B.sub.5, B.sub.4, B.sub.3, B.sub.2, B.sub.1, B.sub.0 ].
(45)
The logic gates in 9/10 encoder 32' perform certain logic functions (given
below) on byte A that effectively "maps" that 9-bit word into a 10-bit
word, C, wherein:
C.DELTA.[C.sub.9, C.sub.8, C.sub.7, C.sub.6, C.sub.5, C.sub.4, C.sub.3,
C.sub.2, C.sub.1, C.sub.0 ] (46)
following the requirements for the selected overall run length constraint
(0, 6/6).
Output latch 34' interleaves word C with 7-bit word B to form a 17-bit
codeword W which satisfies the (0,6/6) constraint, and which is denoted
as:
W.DELTA.[C.sub.9, B.sub.6, C.sub.8, B.sub.5, C.sub.7, C.sub.6, B.sub.4,
C.sub.5, B.sub.3, C.sub.4, B.sub.2, C.sub.3, B.sub.1, C.sub.2, C.sub.1,
B.sub.0, C.sub.0 ]. (47)
Each codeword W includes two subsequences of alternating bits, W.sub.1 and
W.sub.2, wherein the first subsequence W.sub.1 consists only of every
other bit in a codeword W, and the second subsequence W.sub.2 consists of
the remaining bits of that codeword W. The first subsequence W.sub.1 is
denoted as an odd sequence because of having therein the bits from the odd
numbered bit positions in codeword W wherein:
W.sub.1 .DELTA.[C.sub.9, C.sub.8, C.sub.7, B.sub.4, B.sub.3, B.sub.2,
B.sub.1, C.sub.1, C.sub.0 ]. (48)
The remaining bits form the second subsequence W.sub.2 which is denoted as
an even sequence wherein:
W.sub.2 .DELTA.[B.sub.6, B.sub.5, C.sub.6, C.sub.5, C.sub.4, C.sub.3,
C.sub.2, B.sub.0 ]. (49)
In order to ensure that each codeword W satisfies the (0, 6/6) constraint,
the maximum number of consecutive zeros within each codeword W, and across
the boundary between adjacent codewords W in a sequence thereof, is 6.
Again, the maximum number of consecutive zeros within each subsequence
W.sub.1 and W.sub.2, and (a) across the boundary between adjacent
subsequences W.sub.1 in a sequence thereof, and (b) across the boundary
between adjacent subsequences W in a sequence thereof, is 6. Since, again,
it is undesirable to constrain the bits of word B (which would also
effectively place a constraint on the user system since word B is not
being encoded), it is necessary for 9/10 encoder 32' to map word A into
word C such that, in the worst case scenario (when word B is all zeros),
the codeword W will satisfy the (0, 6/6) constraint mentioned above. Since
d=0, the following conditions ensure that the "k" and "i" constraints are
satisfied within each codeword and between consecutive codewords:
C.sub.9 +C.sub.8 +C.sub.7 =1 (50)
C.sub.1 +C.sub.0 =1 (51)
C.sub.8 +C.sub.7 +C.sub.6 +C.sub.5 =1 (52)
C.sub.7 +C.sub.6 +C.sub.5 +C.sub.4 =1 (53)
C.sub.4 +C.sub.3 +C.sub.2 +C.sub.1 =1 (54)
C.sub.5 +C.sub.4 +C.sub.3 =1 (55)
C.sub.8 +C.sub.7 +C.sub.1 =1 (56)
Equations 50 and 51 above ensure that the k=6 constraint is satisfied at
the boundary between codeword W and codewords adjacent thereto since a 1
value for any of C.sub.9, C.sub.8, and C.sub.7 of a codeword W.sub.n and
bits C.sub.1 and C.sub.0 of codeword W.sub.n.+-.1 (see equation 47 above)
effectively limits the length of a string of zeros possible over any 6
consecutive bits (assuming the worst case scenario where word B is zero)
across the boundary between codeword W.sub.n and either of adjacent
codewords W.sub.n.+-.1. Equations 52.+-.55 ensure that within each
codeword W the k=6 constraint is satisfied, since a 1 value of any of bits
C.sub.8, C.sub.7, C.sub.6, C.sub.5, C.sub.4, C.sub.3, C.sub.2 and C.sub.1
of codeword W (equation 47) effectively limits the length of a string of
zeros possible over any 6 consecutive bits (assuming the worst scenario
where word B is al zeros) within that codeword. Equation 54, in
combination with equations 50 and 51, ensures that within each odd
subsequence W.sub.1 and each even subsequence W.sub.2, and at the boundary
between each successive pair of odd subsequence W.sub.1, and between each
successive pair of even subsequence W.sub.2, the i=6 constraint is
satisfied, since, a 1 value for any of bits C.sub.9, C.sub.8, C.sub.7,
C.sub.1 and C.sub.0 of a codeword W effectively limits the length of a
string of zeros possible over any 6 consecutive bits within such
subsequences, and over any 6 consecutive bits bridging across the boundary
between an odd subsequence W.sub.1:n and the subsequences W.sub.1:n.+-.1
adjacent thereto, and between an even subsequence W.sub.2:n and the
subsequences W.sub.2:n.+-.1 adjacent thereto.
There are 524 different 10-bit patterns which satisfy the conditions in
equations 50-56, which is more than the necessary number of 512 (i.e.
2.sup.9) for all possible 9-bit patterns. FIGS. 5A and 5B show a table
representing a one-to-one mapping of any possible value of a 9-bit word A,
taken as a three digit hexadecimal number, into the corresponding 10-bit
word C, taken as a three digit hexadecimal number, such that equations
50-56 are satisfied. The bit patterns are shown in hexadecimal form in
FIG. 4 for simplicity with the least significant (LS) digit in the word A
hexadecimal number represented in the top line and the two most
significant (MS) digits represented in the leftmost column of the table of
FIGS. 5A and 5B.
In order to simplify the implementations of 9/10 encoder 32', the 512
different values for 10-bit initial words C shown in the table of FIGS. 5A
and 5B can be grouped into eight partitions thereof, G, H, J, K, L, M, P
and Q, as shown in FIG. 6 among possible partitioning schemes. In other
words, FIG. 6 is a diagram of the table of FIGS. 5A and 5B in which the
various partitions denoted by one of the capital letters G, H, J, K, L, M,
N, P and Q represent groups of 10-bit C words having a predetermined
relationship to each other described below. All of the definitions of the
logic structure of 9/10 encoder 32' can again be expressed in Boolean
logic expressions wherein ".multidot." denotes an AND gate, "+" denotes an
OR gate, .sym. denotes as exclusive OR gate, and " " denotes a NOT gate.
Referring to FIG. 6, eight partitions of word assignments are identified by
Boolean logic expressions as follows:
G=(A.sub.7 +A.sub.6).multidot.(A.sub.1 +A.sub.0) (57)
H=(A.sub.7 .multidot.A.sub.6).multidot.(A.sub.1 +A.sub.0) (58)
J=(A.sub.5 +A.sub.4).multidot.(A.sub.2 .multidot.A.sub.1
.multidot.A.sub.0).multidot.(A.sub.8 +A.sub.7) (59)
K=A.sub.8 .multidot.(A.sub.5 +A.sub.4).multidot.(A.sub.2 .multidot.A.sub.1
.multidot.A.sub.0) (60)
M=A.sub.8 .multidot.A.sub.7 .multidot.(A.sub.5 +A.sub.4).multidot.A.sub.2
.multidot.A.sub.1 .multidot.A.sub.0 (61)
N=A.sub.8 .multidot.A.sub.7 .multidot.(A.sub.5 +A.sub.4).multidot.A.sub.1
.multidot.A.sub.0 (62)
P=A.sub.8 .multidot.(A.sub.5 .multidot.A.sub.4).multidot.(A.sub.1
.multidot.A.sub.0) (63)
Q=A.sub.8 .multidot.(A.sub.5 .multidot.A.sub.4).multidot.(A.sub.1
.multidot.A.sub.0) (64)
The logical equations for 9/10 encoder 32' for encoding data bits A.sub.8
-A.sub.0 into word bits C.sub.9 -C.sub.0 are given by the following
equations utilizing the eight partitions equations G, H, J, K, L, M, N, P
and Q described above in equations 57-64:
C.sub.9 =G.multidot.A.sub.8 +H.multidot.A.sub.8 +J.multidot.A.sub.3
+K.multidot.A.sub.3 +M.multidot.A.sub.3 +N+P.multidot.A.sub.3 +Q(65)
C.sub.8 =G.multidot.A.sub.7 +H.multidot.A.sub.5 +J+K.multidot.A.sub.7
+M+P(66)
C.sub.7 =G.multidot.A.sub.6 +H+K+P.multidot.A.sub.7 (67)
C.sub.6 =G.multidot.A.sub.5 +H.multidot.A.sub.4 +J.multidot.(A.sub.8
+A.sub.7)+K.multidot.A.sub.6 +M.multidot.A.sub.6 +N.multidot.(A.sub.6
+(A.sub.5 .multidot.A.sub.4))+P.multidot.A.sub.6 +Q.multidot.A.sub.7(68)
C.sub.5 =G.multidot.A.sub.4 +H.multidot.A.sub.3 +J.multidot.A.sub.7
+K+M+N.multidot.[A.sub.6 .multidot.A.sub.5 +(A.sub.6 .multidot.(A.sub.5
+A.sub.4))]+P+Q (69)
C.sub.4 =G+N.multidot.(A.sub.6 .multidot.A.sub.4 +A.sub.6
.multidot.A.sub.4)+Q.multidot.A.sub.6 (70)
C.sub.3 =G.multidot.A.sub.3 +H+J+N (71)
C.sub.2 =G.multidot.A.sub.2 +H.multidot.A.sub.2 +J.multidot.A.sub.6
+K+M+N.multidot.A.sub.3 +Q.multidot.A.sub.3 (72)
C.sub.1 =G.multidot.A.sub.1 +H.multidot.A.sub.1 +J.multidot.A.sub.5
+K.multidot.A.sub.5 +M.multidot.A.sub.5 +N+P+Q (73)
C.sub.0 =G.multidot.A.sub.0 +H.multidot.A.sub.0 +J.multidot.A.sub.4
+K.multidot.A.sub.4 +M.multidot.A.sub.4 +N.multidot.A.sub.2
+P.multidot.A.sub.2 +Q.multidot.A.sub.2 (74)
Referring to FIG. 4, decoder 24' functions to reconstruct the original data
bits A.sub.8 -A.sub.0 and B.sub.6 -B.sub.0 from the codewords W.sub.n
Decoder logic gating 24' identifies the same partition groups as those
used in the encoder (see FIG. 6). Each partition group in 10/9 decoder 54'
can be expressed as a function of code bits C.sub.9 -C.sub.0 as follows:
G=[C.sub.8 .multidot.(C.sub.7 .multidot.C.sub.4)+C.sub.8 .multidot.C.sub.4
].multidot.(C.sub.1 +C.sub.0) (75)
H=(C.sub.7 .multidot.C.sub.4).multidot.C.sub.3 .multidot.(C.sub.1
+C.sub.0)(76)
J=C.sub.8 .multidot.(C.sub.7 .multidot.C.sub.4 .multidot.(C.sub.6
+C.sub.5)).multidot.C.sub.3 .multidot.(C.sub.1 +C.sub.0) (77)
K=(C.sub.7 .multidot.C.sub.5 .multidot.C.sub.4).multidot.(C.sub.3
.multidot.C.sub.2 .multidot.(C.sub.1 +C.sub.0)) (78)
M=C.sub.8 .multidot.(C.sub.7 .multidot.C.sub.4
.multidot.C.sub.5).multidot.C.sub.3 .multidot.C.sub.2 .multidot.(C.sub.1
+C.sub.0) (79)
N=C.sub.9 .multidot.C.sub.8 .multidot.C.sub.7 .multidot.(C.sub.6
+C.sub.5).multidot.C.sub.3 .multidot.C.sub.1 (80)
P=C.sub.8 .multidot.(C.sub.5 .multidot.C.sub.4).multidot.(C.sub.3
.multidot.C.sub.2 .multidot.C.sub.1) (81)
Q=C.sub.9 .multidot.C.sub.8 .multidot.(C.sub.7
.multidot.C.sub.5).multidot.(C.sub.3 .multidot.C.sub.1) (82)
The Boolean logic equations for 10/9 decoder 54' for decoding code bits
C.sub.9 -C.sub.0 into data bits A.sub.7 -A.sub.0 are given by the
following equations utilizing the eight partition equations G, H, I, J. K,
L and M described above in equations 75-82:
A.sub.8 =G.multidot.C.sub.9 +H.multidot.C.sub.9 +J.multidot.(C.sub.6
.multidot.C.sub.5)+M+N+Q (83)
A.sub.7 =G.multidot.C.sub.8 +J.multidot.(C.sub.6
.multidot.C.sub.5)+K.multidot.C.sub.8 +N+P.multidot.C.sub.7
+Q.multidot.C.sub.6 (84)
A.sub.6 =G.multidot.C.sub.7 +J.multidot.C.sub.2 +K.multidot.C.sub.6
+M.multidot.C.sub.6 +N.multidot.C.sub.6 .multidot.(C.sub.5
+C.sub.4)+P.multidot.C.sub.6 +Q.multidot.C.sub.4 (85)
A.sub.5 =G.multidot.C.sub.6 +H.multidot.C.sub.8 +J.multidot.C.sub.1
+K.multidot.C.sub.1 +M.multidot.C.sub.1 +N.multidot.[(C.sub.6
.multidot.C.sub.5 .multidot.C.sub.4)+C.sub.6 .multidot.(C.sub.5 +C.sub.5
.multidot.C.sub.4)] (86)
A.sub.4 =G.multidot.C.sub.5 +H.multidot.C.sub.6 +J.multidot.C.sub.0
+K.multidot.C.sub.0 +M.multidot.C.sub.0 +N.multidot.[(C.sub.6
.multidot.(C.sub.5 +C.sub.5 .multidot.C.sub.4))+(C.sub.6 .multidot.C.sub.5
.multidot.C.sub.4)] (87)
A.sub.3 =G.multidot.C.sub.3 +H.multidot.C.sub.5 +J.multidot.C.sub.9
+K.multidot.C.sub.9 +M.multidot.C.sub.9 +N.multidot. C.sub.2
+P.multidot.C.sub.9 +Q.multidot.C.sub.2 (88)
A.sub.2 =G.multidot.C.sub.2 +H.multidot.C.sub.2 +K+M+N.multidot.C.sub.0
+P.multidot.C.sub.0 +Q.multidot.C.sub.0 (89)
A.sub.1 =G.multidot.C.sub.1 +H.multidot.C.sub.1 (90)
A.sub.0 =G.multidot.C.sub.0 +H.multidot.C.sub.0 (91)
Those skilled in the art will recognize that other partitions may be
chosen, and that further reduced Boolean expressions or other equivalent
expressions, may be obtained from the present logic expressions described
in equations 57-91, and thus that there are other possible logic equations
for both 9/10 encoder 32' and 10/9 decoder 54'.
Although the present invention has been described with reference to
preferred embodiments involving a 16/17 rate RLL code under a (0, 8/6)
constraint and a 16/17 rate RLL code under a (0, 6/6) constraint, workers
skilled in the art will recognize that changes may be made in form and
detail without departing from the spirit and scope of the invention.
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